From owner-dev-commits-src-main@freebsd.org Wed Jun 2 08:05:11 2021 Return-Path: Delivered-To: dev-commits-src-main@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 2D93663DA14; Wed, 2 Jun 2021 08:05:11 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Fw1m70NM5z4YJp; Wed, 2 Jun 2021 08:05:11 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D763F1356E; Wed, 2 Jun 2021 08:05:10 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 15285AjU073064; Wed, 2 Jun 2021 08:05:10 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 15285Alf073063; Wed, 2 Jun 2021 08:05:10 GMT (envelope-from git) Date: Wed, 2 Jun 2021 08:05:10 GMT Message-Id: <202106020805.15285Alf073063@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Marcin Wojtas Subject: git: 4fa977f854e2 - main - sdhci_xenon: add UHS support MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mw X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 4fa977f854e27c93c22acfa6a3ba38f5c4959e15 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-main@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for the main branch of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Jun 2021 08:05:11 -0000 The branch main has been updated by mw: URL: https://cgit.FreeBSD.org/src/commit/?id=4fa977f854e27c93c22acfa6a3ba38f5c4959e15 commit 4fa977f854e27c93c22acfa6a3ba38f5c4959e15 Author: Marcin Wojtas AuthorDate: 2021-05-04 23:47:37 +0000 Commit: Marcin Wojtas CommitDate: 2021-06-02 07:55:20 +0000 sdhci_xenon: add UHS support This patch adds the necessary methods resolution to the sdhci_xenon driver which are required to configure UHS modes for SD/MMC devices. Apart from the two generic routines, the custom sdhci_xenon_set_uhs_timing function is responsible for setting the SDHCI_HOST_CONTROL2 register with appropriate mode select values - in case of HS200 and HS400 they are non-standard. Reviewed by: manu Obtained from: Semihalf Sponsored by: Marvell Differential Revision: https://reviews.freebsd.org/D30565 MFC after: 2 weeks --- sys/dev/sdhci/sdhci_xenon.c | 40 ++++++++++++++++++++++++++++++++++++++++ sys/dev/sdhci/sdhci_xenon.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/sys/dev/sdhci/sdhci_xenon.c b/sys/dev/sdhci/sdhci_xenon.c index 42f36b619b36..3f312921154f 100644 --- a/sys/dev/sdhci/sdhci_xenon.c +++ b/sys/dev/sdhci/sdhci_xenon.c @@ -197,6 +197,43 @@ sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot) return (sdhci_fdt_gpio_get_present(sc->gpio)); } +static void +sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) +{ + const struct mmc_ios *ios; + uint16_t hostctrl2; + + if (slot->version < SDHCI_SPEC_300) + return; + + mtx_assert(&slot->mtx, MA_OWNED); + ios = &slot->host.ios; + + /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */ + hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2); + hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; + if (ios->clock > SD_SDR50_MAX) { + if (ios->timing == bus_timing_mmc_hs400 || + ios->timing == bus_timing_mmc_hs400es) + hostctrl2 |= XENON_CTRL2_MMC_HS400; + else if (ios->timing == bus_timing_mmc_hs200) + hostctrl2 |= XENON_CTRL2_MMC_HS200; + else + hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; + } + else if (ios->clock > SD_SDR25_MAX) + hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; + else if (ios->clock > SD_SDR12_MAX) { + if (ios->timing == bus_timing_uhs_ddr50 || + ios->timing == bus_timing_mmc_ddr52) + hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; + else + hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; + } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) + hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; + sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2); +} + static int sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) { @@ -663,6 +700,8 @@ static device_method_t sdhci_xenon_methods[] = { DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), + DEVMETHOD(mmcbr_tune, sdhci_generic_tune), + DEVMETHOD(mmcbr_retune, sdhci_generic_retune), /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), @@ -674,6 +713,7 @@ static device_method_t sdhci_xenon_methods[] = { DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present), + DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing), DEVMETHOD_END }; diff --git a/sys/dev/sdhci/sdhci_xenon.h b/sys/dev/sdhci/sdhci_xenon.h index b79dab6bab55..07ed99339b8d 100644 --- a/sys/dev/sdhci/sdhci_xenon.h +++ b/sys/dev/sdhci/sdhci_xenon.h @@ -46,6 +46,10 @@ #define XENON_ENABLE_DATA_STROBE (1 << 24) #define XENON_ENABLE_RESP_STROBE (1 << 25) +/* Custom HS200 / HS400 Mode Select values in SDHCI_HOST_CONTROL2 register. */ +#define XENON_CTRL2_MMC_HS200 0x5 +#define XENON_CTRL2_MMC_HS400 0x6 + /* eMMC PHY */ #define XENON_EMMC_PHY_REG_BASE 0x170