Date: Tue, 18 Mar 2014 08:07:04 -0600 From: Warner Losh <imp@bsdimp.com> To: Adrian Chadd <adrian@FreeBSD.org> Cc: "freebsd-embedded@freebsd.org" <freebsd-embedded@freebsd.org> Subject: Re: nand controller - how should one handle controllers that want the command+address bits together? Message-ID: <72611BD5-E115-497D-82FC-3C1065E8A3F5@bsdimp.com> In-Reply-To: <CAJ-VmonpUsvXFHMCyH--3S4AEocTjhESCyjp9UmT-w5GyuZmvw@mail.gmail.com> References: <CAJ-VmonpUsvXFHMCyH--3S4AEocTjhESCyjp9UmT-w5GyuZmvw@mail.gmail.com>
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On Mar 18, 2014, at 5:35 AM, Adrian Chadd <adrian@FreeBSD.org> wrote: > Hiya, >=20 > I've got the atheros ar934x nand controller bits looking like they're > working on freebsd-head enough to send/receive a READID command with > an address of 0x0. However, the NAND controller sends commands with > the cmd and address phases as part of the command, rather than calling > send_command / send_address methods called multiple times. >=20 > It seems like our nandbus and nand controller layer is a very thin > shim over what the NAND control messages look like, rather than some > higher level 'thing' that allows for slightly more intelligent (read: > DMA/ECC capable) hardware. >=20 > So, what gives? Our NAND layer is very thin. The early controllers that were targeted by = the NAND controller were rather dump, little more than bit-bang controllers that = could modulate ALE and CLE as needed. There=92s no provision for DMA, at all = really. There=92s very little provision for ECC, since that=92s usually done as = part of the DMA operation. I=92m surprised you haven=92t complained about the excruciatingly long = busy waits yet. Our complete ignoring of the B/NR signal. The lack of any kind of = interrupt attempts for the GPIO pins we=92re driving, the hardwired state machines for the = NAND that just happen to work with the older generation parts but will encounter issues = on the latest NAND. Warner
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