From owner-freebsd-bugs  Sat Mar 13  1:10:31 1999
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Date: Sat, 13 Mar 1999 01:10:03 -0800 (PST)
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From: "Daniel C. Sobral" <dcs@newsguy.com>
Subject: Re: kern/10565: Slow timekeeping on certain motherboards/cpus/chipsets
Reply-To: "Daniel C. Sobral" <dcs@newsguy.com>
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The following reply was made to PR kern/10565; it has been noted by GNATS.

From: "Daniel C. Sobral" <dcs@newsguy.com>
To: junki@qn-lpr2-98.quicknet.inet.fi
Cc: FreeBSD-gnats-submit@FreeBSD.ORG
Subject: Re: kern/10565: Slow timekeeping on certain motherboards/cpus/chipsets
Date: Sat, 13 Mar 1999 17:57:12 +0900

 Would you happen to have apm enabled in these computers?
 
 Juha Nurmela wrote:
 > 
 > >Number:         10565
 > >Category:       kern
 > >Synopsis:       Slow timekeeping on certain motherboards/cpus/chipsets
 > >Confidential:   no
 > >Severity:       non-critical
 > >Priority:       low
 > >Responsible:    freebsd-bugs
 > >State:          open
 > >Quarter:
 > >Keywords:
 > >Date-Required:
 > >Class:          change-request
 > >Submitter-Id:   current-users
 > >Arrival-Date:   Fri Mar 12 19:30:00 PST 1999
 > >Closed-Date:
 > >Last-Modified:
 > >Originator:     Juha Nurmela
 > >Release:        FreeBSD 4.0-CURRENT i386
 > >Organization:
 > ACME Inc.
 > >Environment:
 > 
 >         Timecounter "i8254"  frequency 1193182 Hz
 >         Timecounter "TSC"  frequency 74539244 Hz
 >         CPU: AMD K5 model 0 (74.54-MHz 586-class CPU)
 >                 Origin = "AuthenticAMD"  Id = 0x500  Stepping=0
 >                 Features=0x3bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,APIC>
 > 
 >         chip0: <Intel 82437VX PCI cache memory controller> rev 0x02 on pci0.0.0
 >         chip1: <Intel 82371SB PCI to ISA bridge> rev 0x01 on pci0.7.0
 > 
 > >Description:
 > 
 >         Time does not increment. Well, very slowly and not in any determinable
 >         constant rate. Using the timerchip for timecounter instead
 >         of tsc register works around the problem.
 > 
 >         Another 'fix' with my mobo is to keep the cpu busy, and not let
 >         it enter HLT. 'while : ; do date; done' almost does the trick as
 >         well as a idle-priority process in tight loop (does it better).
 > 
 >         Looks like the mobo does bad SMI stuff whenever a HLT is executed,
 >         and it cannot really be changed in the bios settings which disable
 >         power management.
 > 
 > >How-To-Repeat:
 > 
 >         With this kind of PC, build a kernel which contains no apm0,
 >         nor SMP, and watch date in idlish system, then in busyish system.
 >         Date should step almost properly in busy state and halt
 >         almost completely in idle system.
 > 
 > >Fix:
 > 
 >         It might be nice to have a std way to set the existing hlt_vector in
 >         swtch.s into just RET (which it already is with SMP).
 >                 options "CPU_HALT_NO" and/or
 >                 sysctl -w machdep.do_halt=0
 >         cp_time[] via sysctl would be nice too...
 > 
 > >Release-Note:
 > >Audit-Trail:
 > >Unformatted:
 > 
 > To Unsubscribe: send mail to majordomo@FreeBSD.org
 > with "unsubscribe freebsd-bugs" in the body of the message
 
 --
 Daniel C. Sobral			(8-DCS)
 dcs@newsguy.com
 dcs@freebsd.org
 
 	"My theory is that his ignorance clouded his poor judgment."
 
 


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