From owner-cvs-src@FreeBSD.ORG  Fri May 23 16:16:44 2003
Return-Path: <owner-cvs-src@FreeBSD.ORG>
Delivered-To: cvs-src@freebsd.org
Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125])
	by hub.freebsd.org (Postfix) with ESMTP
	id 0251A37B401; Fri, 23 May 2003 16:16:44 -0700 (PDT)
Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115])
	by mx1.FreeBSD.org (Postfix) with ESMTP
	id A740043F3F; Fri, 23 May 2003 16:16:43 -0700 (PDT)
	(envelope-from marcel@FreeBSD.org)
Received: from repoman.freebsd.org (localhost [127.0.0.1])
	by repoman.freebsd.org (8.12.6/8.12.6) with ESMTP id h4NNGh0U096193;
	Fri, 23 May 2003 16:16:43 -0700 (PDT)
	(envelope-from marcel@repoman.freebsd.org)
Received: (from marcel@localhost)
	by repoman.freebsd.org (8.12.6/8.12.6/Submit) id h4NNGhpc096192;
	Fri, 23 May 2003 16:16:43 -0700 (PDT)
Message-Id: <200305232316.h4NNGhpc096192@repoman.freebsd.org>
From: Marcel Moolenaar <marcel@FreeBSD.org>
Date: Fri, 23 May 2003 16:16:43 -0700 (PDT)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org,
	cvs-all@FreeBSD.org
X-FreeBSD-CVS-Branch: HEAD
Subject: cvs commit: src/sys/ia64/ia64 context.s
X-BeenThere: cvs-src@freebsd.org
X-Mailman-Version: 2.1.1
Precedence: list
List-Id: CVS commit messages for the src tree <cvs-src.freebsd.org>
List-Unsubscribe: <http://lists.freebsd.org/mailman/listinfo/cvs-src>,
	<mailto:cvs-src-request@freebsd.org?subject=unsubscribe>
List-Archive: <http://lists.freebsd.org/pipermail/cvs-src>
List-Post: <mailto:cvs-src@freebsd.org>
List-Help: <mailto:cvs-src-request@freebsd.org?subject=help>
List-Subscribe: <http://lists.freebsd.org/mailman/listinfo/cvs-src>,
	<mailto:cvs-src-request@freebsd.org?subject=subscribe>
X-List-Received-Date: Fri, 23 May 2003 23:16:44 -0000

marcel      2003/05/23 16:16:43 PDT

  FreeBSD src repository

  Modified files:
    sys/ia64/ia64        context.s 
  Log:
  In swapctx(), put the RSE in enforced lazy mode before we flush the
  register stack. There's nothing really wrong with flushing before
  putting the RSE in enforced lazy mode, provided you don't depend on
  ar.bspstore being equal to ar.bsp when the RSE has been put in
  enforced lazy more. The small window between the flush and setting
  the RSE may be sufficient to have the RSE eagerly increase the dirty
  region (and hence cause ar.bspstore != ar.bsp) or have an interrupt
  that may even get the laziest RSE to do something.
  
  Anyway: we don't depend on ar.bspstore being equal to ar.bsp, so
  nothing was and is broken. But the code was non-intuitive and
  easily confuses. This is a source of future bugs.
  
  Note: the advantage of not depending on ar.bspstore is that there's
  some recilience against an interrupted flushrs. Clobbering is limited
  to stacked register contents only, not to RSE address clobbering.
  
  Approved: re@ (blanket)
  
  Revision  Changes    Path
  1.2       +2 -2      src/sys/ia64/ia64/context.s