From owner-freebsd-arch@FreeBSD.ORG Fri Mar 13 18:31:09 2015 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 8F9AAEF6; Fri, 13 Mar 2015 18:31:09 +0000 (UTC) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 66C1FA1; Fri, 13 Mar 2015 18:31:09 +0000 (UTC) Received: from ralph.baldwin.cx (pool-173-54-116-245.nwrknj.fios.verizon.net [173.54.116.245]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 59A2DB945; Fri, 13 Mar 2015 14:31:08 -0400 (EDT) From: John Baldwin To: Adrian Chadd Subject: Re: RFC: Simplfying hyperthreading distinctions Date: Fri, 13 Mar 2015 13:53:40 -0400 Message-ID: <2652866.1YVC5LhOC2@ralph.baldwin.cx> User-Agent: KMail/4.14.2 (FreeBSD/10.1-STABLE; KDE/4.14.2; amd64; ; ) In-Reply-To: References: <1640664.8z9mx3EOQs@ralph.baldwin.cx> <2092193.qt8NhEKglv@ralph.baldwin.cx> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Fri, 13 Mar 2015 14:31:08 -0400 (EDT) Cc: Andriy Gapon , "freebsd-arch@freebsd.org" X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Mar 2015 18:31:09 -0000 On Friday, March 06, 2015 03:45:13 PM Adrian Chadd wrote: > Hi! > > Hm, I looked at this: > > https://en.wikipedia.org/wiki/Bonnell_%28microarchitecture%29 > > .. and thought it was old-school HTT. If it's not old-school HTT then cool. It is not. The SDM manuals explicitly differentiate Atom CPUs from Pentium 4 when talking about HTT (oddly they don't really mention Core-based CPUs I believe because new HTT first showed up in Atoms and they never bothered to update that part of the SDM?). -- John Baldwin