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[209.85.166.50]) by smtp.gmail.com with ESMTPSA id b17sm21469444ion.0.2019.04.17.10.30.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 10:30:49 -0700 (PDT) Received: by mail-io1-f50.google.com with SMTP id v4so21283220ioj.5; Wed, 17 Apr 2019 10:30:49 -0700 (PDT) X-Received: by 2002:a6b:691a:: with SMTP id e26mr31309579ioc.124.1555522249032; Wed, 17 Apr 2019 10:30:49 -0700 (PDT) MIME-Version: 1.0 References: <201904162251.x3GMp2aF097103@gndrsh.dnsmgr.net> <4d6b8a14-b053-9ed1-14b2-bbc359ac9413@FreeBSD.org> <48b25255-3d66-69fc-658b-6176ebaf4640@FreeBSD.org> In-Reply-To: <48b25255-3d66-69fc-658b-6176ebaf4640@FreeBSD.org> Reply-To: cem@freebsd.org From: Conrad Meyer X-Gmail-Original-Message-ID: Message-ID: Subject: Re: svn commit: r346250 - in head: share/man/man4 share/man/man9 sys/dev/random sys/kern sys/libkern sys/sys To: John Baldwin Cc: src-committers , svn-src-all , svn-src-head Content-Type: text/plain; charset="UTF-8" Precedence: bulk X-Loop: FreeBSD.org Sender: owner-src-committers@freebsd.org X-Rspamd-Queue-Id: 86FE48A332 X-Spamd-Bar: ------ Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-6.98 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.98)[-0.981,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; REPLY(-4.00)[] Status: O X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Date: Tue, 03 Sep 2019 14:07:16 -0000 X-Original-Date: Wed, 17 Apr 2019 10:30:38 -0700 X-List-Received-Date: Tue, 03 Sep 2019 14:07:16 -0000 On Wed, Apr 17, 2019 at 9:06 AM John Baldwin wrote: > > On 4/16/19 4:48 PM, Conrad Meyer wrote: > > Perhaps cryptographically random stack-protector cookies are simply > > inappropriate for MIPS or RISCV. Do we have any other examples of > > kernel random consumers blocking after that immediate hiccup is > > overcome? > > There may be MIPS and RISCV designs that do have suitable entropy available > (especially I would expect future RISCV designs to have them), so I think > blacklisting stack protector wholesale on those architectures is overboard. The difficulty is how early __stack_chk_init runs vs when entropy might be available. If some MIPS or RISCV design shows up with a fast HWRNG source, great! > I think some sort of off-by-default knob (even a compile option) is fine for > people who need fast and loose vs safe as you already agreed to earlier. > > Also, for development testing we still want coverage of using stack cookies > on MIPS and RISCV even if the simulator environment gives not-very-strong > cookie values. Right. There's a difference between removing random stack cookies and removing stack cookies entirely; I agree some benefit remains for development. Best, Conrad