From owner-svn-src-all@FreeBSD.ORG Tue Nov 2 12:42:47 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id F2BBC1065695; Tue, 2 Nov 2010 12:42:46 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id DEFE18FC16; Tue, 2 Nov 2010 12:42:46 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oA2CgkUK045843; Tue, 2 Nov 2010 12:42:46 GMT (envelope-from jhb@svn.freebsd.org) Received: (from jhb@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oA2CgkIh045841; Tue, 2 Nov 2010 12:42:46 GMT (envelope-from jhb@svn.freebsd.org) Message-Id: <201011021242.oA2CgkIh045841@svn.freebsd.org> From: John Baldwin Date: Tue, 2 Nov 2010 12:42:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-6@freebsd.org X-SVN-Group: stable-6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r214674 - stable/6/sys/dev/ata X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Nov 2010 12:42:47 -0000 Author: jhb Date: Tue Nov 2 12:42:46 2010 New Revision: 214674 URL: http://svn.freebsd.org/changeset/base/214674 Log: MFC: Use the 'cfg2' value for Intel chipsets to limit the number of channels for non-SATA controllers. Specifically, limit the non-AHCI ICH7, 63XXESB2, and ICHM8 controllers to a single channel. Modified: stable/6/sys/dev/ata/ata-chipset.c Modified: stable/6/sys/dev/ata/ata-chipset.c ============================================================================== --- stable/6/sys/dev/ata/ata-chipset.c Tue Nov 2 12:40:13 2010 (r214673) +++ stable/6/sys/dev/ata/ata-chipset.c Tue Nov 2 12:42:46 2010 (r214674) @@ -1762,58 +1762,58 @@ ata_intel_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); static struct ata_chip_id ids[] = - {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, - { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, - { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, - { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, - { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, - { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, - { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, - { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, - { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, - { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, - { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, - { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, - { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, - { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, - { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, - { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, - { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, - { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, - { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, - { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, - { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, - { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, - { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, - { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, - { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, - { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, - { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, - { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, - { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, - { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, - { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, - { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, - { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, - { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, - { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, - { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, - { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, - { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, - { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, - { ATA_I82801HBM, 0, 0, 0x00, ATA_UDMA5, "ICH8M" }, - { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA150, "ICH8M" }, - { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, - { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, - { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I82801IB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, - { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, + {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, + { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, + { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, + { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, + { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, + { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, + { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, + { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, + { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, + { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, + { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, + { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, + { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, + { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, + { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, + { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" }, + { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" }, + { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, + { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" }, + { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" }, + { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, + { ATA_I82801FB_S1, 0, AHCI, 0, ATA_SA150, "ICH6" }, + { ATA_I82801FB_R1, 0, AHCI, 0, ATA_SA150, "ICH6" }, + { ATA_I82801FBM, 0, AHCI, 0, ATA_SA150, "ICH6M" }, + { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, + { ATA_I82801GB_S1, 0, AHCI, 0, ATA_SA300, "ICH7" }, + { ATA_I82801GB_R1, 0, AHCI, 0, ATA_SA300, "ICH7" }, + { ATA_I82801GB_AH, 0, AHCI, 0, ATA_SA300, "ICH7" }, + { ATA_I82801GBM_S1, 0, AHCI, 0, ATA_SA300, "ICH7M" }, + { ATA_I82801GBM_R1, 0, AHCI, 0, ATA_SA300, "ICH7M" }, + { ATA_I82801GBM_AH, 0, AHCI, 0, ATA_SA300, "ICH7M" }, + { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, + { ATA_I63XXESB2_S1, 0, AHCI, 0, ATA_SA300, "63XXESB2" }, + { ATA_I63XXESB2_S2, 0, AHCI, 0, ATA_SA300, "63XXESB2" }, + { ATA_I63XXESB2_R1, 0, AHCI, 0, ATA_SA300, "63XXESB2" }, + { ATA_I63XXESB2_R2, 0, AHCI, 0, ATA_SA300, "63XXESB2" }, + { ATA_I82801HB_S1, 0, AHCI, 0, ATA_SA300, "ICH8" }, + { ATA_I82801HB_S2, 0, AHCI, 0, ATA_SA300, "ICH8" }, + { ATA_I82801HB_R1, 0, AHCI, 0, ATA_SA300, "ICH8" }, + { ATA_I82801HB_AH4, 0, AHCI, 0, ATA_SA300, "ICH8" }, + { ATA_I82801HB_AH6, 0, AHCI, 0, ATA_SA300, "ICH8" }, + { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, + { ATA_I82801HBM_S1, 0, 0, 0, ATA_SA150, "ICH8M" }, + { ATA_I82801HBM_S2, 0, AHCI, 0, ATA_SA300, "ICH8M" }, + { ATA_I82801HBM_S3, 0, AHCI, 0, ATA_SA300, "ICH8M" }, + { ATA_I82801IB_S1, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I82801IB_S2, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I82801IB_AH2, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I82801IB_AH4, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I82801IB_AH6, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I82801IB_R1, 0, AHCI, 0, ATA_SA300, "ICH9" }, + { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, { 0, 0, 0, 0, 0, 0}}; if (!(ctlr->chip = ata_match_chip(dev, ids))) @@ -1855,6 +1855,7 @@ ata_intel_chipinit(device_t dev) /* non SATA intel chips goes here */ else if (ctlr->chip->max_dma < ATA_SA150) { + ctlr->channels = ctlr->chip->cfg2; ctlr->allocate = ata_intel_allocate; ctlr->setmode = ata_intel_new_setmode; }