From owner-svn-src-head@freebsd.org Tue Jun 13 18:55:22 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C2ACABFC373; Tue, 13 Jun 2017 18:55:22 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 99CD13871; Tue, 13 Jun 2017 18:55:22 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v5DItLgf035075; Tue, 13 Jun 2017 18:55:21 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v5DItLpT035073; Tue, 13 Jun 2017 18:55:21 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201706131855.v5DItLpT035073@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Tue, 13 Jun 2017 18:55:21 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r319914 - in head/sys: arm/mv boot/fdt/dts/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2017 18:55:22 -0000 Author: zbb Date: Tue Jun 13 18:55:21 2017 New Revision: 319914 URL: https://svnweb.freebsd.org/changeset/base/319914 Log: Enable HWPMC overflow IRQ on both CPUs in MPIC This commit enables usage of HWPMC interrupts for the Marvell SoCs, which use MPIC (Armada38x and ArmadaXP). Those interrupts require extra unmasking, comparing to others. Also, in order to process counters per-CPU, they are masked/unmasked using separate registers' sets for each core. Submitted by: Michal Mazur Marcin Wojtas Obtained from: Semihalf Sponsored by: Stormshield, Netgate Differential revision: https://reviews.freebsd.org/D10913 Modified: head/sys/arm/mv/mpic.c head/sys/boot/fdt/dts/arm/armada-38x.dtsi Modified: head/sys/arm/mv/mpic.c ============================================================================== --- head/sys/arm/mv/mpic.c Tue Jun 13 18:53:56 2017 (r319913) +++ head/sys/arm/mv/mpic.c Tue Jun 13 18:55:21 2017 (r319914) @@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include @@ -70,6 +71,7 @@ __FBSDID("$FreeBSD$"); #define debugf(fmt, args...) #endif +#define MPIC_INT_LOCAL 3 #define MPIC_INT_ERR 4 #define MPIC_INT_MSI 96 @@ -93,7 +95,9 @@ __FBSDID("$FreeBSD$"); #define MPIC_IIACK 0x44 #define MPIC_ISM 0x48 #define MPIC_ICM 0x4c -#define MPIC_ERR_MASK 0xe50 +#define MPIC_ERR_MASK 0x50 +#define MPIC_LOCAL_MASK 0x54 +#define MPIC_CPU(n) (n) * 0x100 #define MPIC_PPI 32 @@ -223,6 +227,7 @@ mv_mpic_attach(device_t dev) struct mv_mpic_softc *sc; int error; uint32_t val; + int cpu; sc = (struct mv_mpic_softc *)device_get_softc(dev); @@ -283,6 +288,12 @@ mv_mpic_attach(device_t dev) mpic_unmask_msi(); + /* Unmask CPU performance counters overflow irq */ + for (cpu = 0; cpu < mp_ncpus; cpu++) + MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK, + (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc, + MPIC_CPU(cpu) + MPIC_LOCAL_MASK)); + return (0); } @@ -488,6 +499,16 @@ static void mpic_unmask_irq(uintptr_t nb) { +#ifdef SMP + int cpu; + + if (nb == MPIC_INT_LOCAL) { + for (cpu = 0; cpu < mp_ncpus; cpu++) + MPIC_CPU_WRITE(mv_mpic_sc, + MPIC_CPU(cpu) + MPIC_ICM, nb); + return; + } +#endif if (mpic_irq_is_percpu(nb)) MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); else if (nb < ERR_IRQ) @@ -503,6 +524,16 @@ static void mpic_mask_irq(uintptr_t nb) { +#ifdef SMP + int cpu; + + if (nb == MPIC_INT_LOCAL) { + for (cpu = 0; cpu < mp_ncpus; cpu++) + MPIC_CPU_WRITE(mv_mpic_sc, + MPIC_CPU(cpu) + MPIC_ISM, nb); + return; + } +#endif if (mpic_irq_is_percpu(nb)) MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); else if (nb < ERR_IRQ) Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi ============================================================================== --- head/sys/boot/fdt/dts/arm/armada-38x.dtsi Tue Jun 13 18:53:56 2017 (r319913) +++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi Tue Jun 13 18:55:21 2017 (r319914) @@ -419,7 +419,7 @@ mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21870 0x58>; + reg = <0x20a00 0x2d0>, <0x21870 0x300>; #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller;