From owner-dev-commits-src-main@freebsd.org Thu May 6 01:57:52 2021 Return-Path: Delivered-To: dev-commits-src-main@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id CB4F162E999; Thu, 6 May 2021 01:57:52 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4FbGtm5P2lz3HYP; Thu, 6 May 2021 01:57:52 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id AC1587F2E; Thu, 6 May 2021 01:57:52 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1461vq2j026775; Thu, 6 May 2021 01:57:52 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1461vqQq026774; Thu, 6 May 2021 01:57:52 GMT (envelope-from git) Date: Thu, 6 May 2021 01:57:52 GMT Message-Id: <202105060157.1461vqQq026774@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Justin Hibbits Subject: git: 664057961085 - main - msun fixes for SPE MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jhibbits X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6640579610856168a64e12c097ce012c46648e00 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-main@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for the main branch of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 May 2021 01:57:52 -0000 The branch main has been updated by jhibbits: URL: https://cgit.FreeBSD.org/src/commit/?id=6640579610856168a64e12c097ce012c46648e00 commit 6640579610856168a64e12c097ce012c46648e00 Author: Justin Hibbits AuthorDate: 2021-05-05 14:20:56 +0000 Commit: Justin Hibbits CommitDate: 2021-05-06 01:57:33 +0000 msun fixes for SPE Summary: Fix FPU exception management for powerpcspe. Bits are in a different place from the standard FPSCR, so we need to handle the shifting differences. Also, there's no concept of a "software exception" raise, so we need to do exceptional math to trigger the exception from software. Reviewed By: alfredo Differential Revision: https://reviews.freebsd.org/D22824 --- lib/msun/powerpc/fenv.c | 30 ++++++++++++++++++++++++++++++ lib/msun/powerpc/fenv.h | 19 ++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/lib/msun/powerpc/fenv.c b/lib/msun/powerpc/fenv.c index b7e611ed99a0..7f7d98515995 100644 --- a/lib/msun/powerpc/fenv.c +++ b/lib/msun/powerpc/fenv.c @@ -30,6 +30,10 @@ #define __fenv_static #include "fenv.h" +#ifdef __SPE__ +#include +#include +#endif #ifdef __GNUC_GNU_INLINE__ #error "This file must be compiled with C99 'inline' semantics" @@ -40,7 +44,9 @@ const fenv_t __fe_dfl_env = 0x00000000; extern inline int feclearexcept(int __excepts); extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts); extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts); +#ifndef __SPE__ extern inline int feraiseexcept(int __excepts); +#endif extern inline int fetestexcept(int __excepts); extern inline int fegetround(void); extern inline int fesetround(int __round); @@ -48,3 +54,27 @@ extern inline int fegetenv(fenv_t *__envp); extern inline int feholdexcept(fenv_t *__envp); extern inline int fesetenv(const fenv_t *__envp); extern inline int feupdateenv(const fenv_t *__envp); + +#ifdef __SPE__ +#define PMAX 0x7f7fffff +#define PMIN 0x00800000 +int feraiseexcept(int __excepts) +{ + uint32_t spefscr; + + spefscr = mfspr(SPR_SPEFSCR); + mtspr(SPR_SPEFSCR, spefscr | (__excepts & FE_ALL_EXCEPT)); + + if (__excepts & FE_INVALID) + __asm __volatile ("efsdiv %0, %0, %1" :: "r"(0), "r"(0)); + if (__excepts & FE_DIVBYZERO) + __asm __volatile ("efsdiv %0, %0, %1" :: "r"(1.0f), "r"(0)); + if (__excepts & FE_UNDERFLOW) + __asm __volatile ("efsmul %0, %0, %0" :: "r"(PMIN)); + if (__excepts & FE_OVERFLOW) + __asm __volatile ("efsadd %0, %0, %0" :: "r"(PMAX)); + if (__excepts & FE_INEXACT) + __asm __volatile ("efssub %0, %0, %1" :: "r"(PMIN), "r"(1.0f)); + return (0); +} +#endif diff --git a/lib/msun/powerpc/fenv.h b/lib/msun/powerpc/fenv.h index d054220678c2..21a70df3d104 100644 --- a/lib/msun/powerpc/fenv.h +++ b/lib/msun/powerpc/fenv.h @@ -42,6 +42,17 @@ typedef __uint32_t fenv_t; typedef __uint32_t fexcept_t; /* Exception flags */ +#ifdef __SPE__ +#define FE_OVERFLOW 0x00000100 +#define FE_UNDERFLOW 0x00000200 +#define FE_DIVBYZERO 0x00000400 +#define FE_INVALID 0x00000800 +#define FE_INEXACT 0x00001000 + +#define FE_ALL_INVALID FE_INVALID + +#define _FPUSW_SHIFT 6 +#else #define FE_INEXACT 0x02000000 #define FE_DIVBYZERO 0x04000000 #define FE_UNDERFLOW 0x08000000 @@ -67,6 +78,9 @@ typedef __uint32_t fexcept_t; #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ FE_VXSNAN | FE_INVALID) + +#define _FPUSW_SHIFT 22 +#endif #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) @@ -85,7 +99,6 @@ extern const fenv_t __fe_dfl_env; #define FE_DFL_ENV (&__fe_dfl_env) /* We need to be able to map status flag positions to mask flag positions */ -#define _FPUSW_SHIFT 22 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) @@ -156,6 +169,9 @@ fesetexceptflag(const fexcept_t *__flagp, int __excepts) return (0); } +#ifdef __SPE__ +extern int feraiseexcept(int __excepts); +#else __fenv_static inline int feraiseexcept(int __excepts) { @@ -168,6 +184,7 @@ feraiseexcept(int __excepts) __mtfsf(__r); return (0); } +#endif __fenv_static inline int fetestexcept(int __excepts)