From owner-p4-projects@FreeBSD.ORG Mon Sep 8 04:53:57 2014 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 161C4FB; Mon, 8 Sep 2014 04:53:57 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 4DE25532 for ; Mon, 8 Sep 2014 04:52:26 +0000 (UTC) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:1900:2254:2068::682:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 3050A1FF3 for ; Mon, 8 Sep 2014 04:52:26 +0000 (UTC) Received: from skunkworks.freebsd.org ([127.0.1.74]) by skunkworks.freebsd.org (8.14.9/8.14.9) with ESMTP id s884qQfG029640 for ; Mon, 8 Sep 2014 04:52:26 GMT (envelope-from jhb@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.9/8.14.9/Submit) id s884qQtV029637 for perforce@freebsd.org; Mon, 8 Sep 2014 04:52:26 GMT (envelope-from jhb@freebsd.org) Date: Mon, 8 Sep 2014 04:52:26 GMT Message-Id: <201409080452.s884qQtV029637@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to jhb@freebsd.org using -f From: John Baldwin Subject: PERFORCE change 1199789 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.18-1 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Sep 2014 04:53:57 -0000 http://p4web.freebsd.org/@@1199789?ac=10 Change 1199789 by jhb@jhb_ralph on 2014/09/04 01:56:54 Trim trailing whitespace. Affected files ... .. //depot/projects/smpng/sys/amd64/amd64/identcpu.c#55 edit .. //depot/projects/smpng/sys/i386/i386/identcpu.c#82 edit Differences ... ==== //depot/projects/smpng/sys/amd64/amd64/identcpu.c#55 (text+ko) ==== @@ -97,11 +97,11 @@ NULL, 0, sysctl_hw_machine, "A", "Machine class"); static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, +SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model"); static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, +SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, &hw_clockrate, 0, "CPU instruction clock rate"); static eventhandler_tag tsc_post_tag; @@ -686,15 +686,15 @@ printf("L2 unified cache: %d kbytes", regs[2] >> 16); printf(", %d bytes/line", regs[2] & 0xff); printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); + print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); } /* - * Opteron Rev E shows a bug as in very rare occasions a read memory - * barrier is not performed as expected if it is followed by a - * non-atomic read-modify-write instruction. + * Opteron Rev E shows a bug as in very rare occasions a read memory + * barrier is not performed as expected if it is followed by a + * non-atomic read-modify-write instruction. * As long as that bug pops up very rarely (intensive machine usage - * on other operating systems generally generates one unexplainable + * on other operating systems generally generates one unexplainable * crash any 2 months) and as long as a model specific fix would be * impratical at this stage, print out a warning string if the broken * model and family are identified. @@ -910,7 +910,7 @@ "\012single" /* INVVPID single-context type */ "\013all" /* INVVPID all-context type */ /* INVVPID single-context-retaining-globals type */ - "\014single-globals" + "\014single-globals" ); } } ==== //depot/projects/smpng/sys/i386/i386/identcpu.c#82 (text+ko) ==== @@ -75,15 +75,15 @@ int cpu_class; char machine[] = MACHINE; -SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class"); static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, +SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model"); static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, +SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, &hw_clockrate, 0, "CPU instruction clock rate"); static eventhandler_tag tsc_post_tag; @@ -1270,7 +1270,7 @@ printf("L2 internal cache: %d kbytes", regs[2] >> 16); printf(", %d bytes/line", regs[2] & 0xff); printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_assoc((regs[2] >> 12) & 0x0f); + print_AMD_assoc((regs[2] >> 12) & 0x0f); } } if (((cpu_id & 0xf00) == 0x500)