Date: Tue, 6 Feb 2007 11:26:42 GMT From: Edwin Mons<freebsd@edwinm.ik.nu> To: freebsd-gnats-submit@FreeBSD.org Subject: i386/108830: Add support for nForce MCP61 chipset Message-ID: <200702061126.l16BQgxx093898@www.freebsd.org> Resent-Message-ID: <200702061130.l16BUGnb041596@freefall.freebsd.org>
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>Number: 108830
>Category: i386
>Synopsis: Add support for nForce MCP61 chipset
>Confidential: no
>Severity: non-critical
>Priority: medium
>Responsible: freebsd-i386
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: change-request
>Submitter-Id: current-users
>Arrival-Date: Tue Feb 06 11:30:15 GMT 2007
>Closed-Date:
>Last-Modified:
>Originator: Edwin Mons
>Release: 6.2-RELEASE
>Organization:
IK.NU
>Environment:
FreeBSD mag5.ik.nu 6.2-RELEASE FreeBSD 6.2-RELEASE #4: Sun Feb 4 13:22:25 CET 2007 root@mag5.ik.nu:/usr/obj/usr/src/sys/MAG-V i386
>Description:
Newer nForce chipsets made by nvidia are not yet supported by FreeBSD. The attached patch adds the device id's of the smbus controller, ata controllers and NIC of the MCP61 (amongst others).
The MCP19 version of the nForce NIC appears to have the MAC address stored in the correct order. Documentation suggests that others do not need the reversal, either. According to the Linux forcedeth.c driver, there's a bit (0x0008000) in the NvRegTransmitPoll register (base + 0x10c) in the PCI configuration, but I'm afraid I don't really know how to add this in FreeBSD. The hardcoded check on the MCP19 is certainly not the one that should be used if this is added to the tree.
One thing I noticed with the nve on my chipset (nForce 6600 + 405), is that using NFS over UDP results in an almost instant panic (when writing a 256MB file, only 2~3 MB is received at the remote and before the machine crashes with a register dump). NFS over TCP is rock solid.
>How-To-Repeat:
>Fix:
Patch attached with submission follows:
--- ./dev/ata/ata-pci.h.orig Sat Feb 3 22:09:45 2007
+++ ./dev/ata/ata-pci.h Sat Feb 3 22:11:20 2007
@@ -211,16 +211,19 @@
#define ATA_NFORCE_CK804_S1 0x005410de
#define ATA_NFORCE_CK804_S2 0x005510de
#define ATA_NFORCE_MCP51 0x026510de
#define ATA_NFORCE_MCP51_S1 0x026610de
#define ATA_NFORCE_MCP51_S2 0x026710de
#define ATA_NFORCE_MCP55 0x036e10de
#define ATA_NFORCE_MCP55_S1 0x037e10de
#define ATA_NFORCE_MCP55_S2 0x037f10de
+#define ATA_NFORCE_MCP61 0x03ec10de
+#define ATA_NFORCE_MCP61_S1 0x03f610de
+#define ATA_NFORCE_MCP61_S2 0x03f710de
#define ATA_PROMISE_ID 0x105a
#define ATA_PDC20246 0x4d33105a
#define ATA_PDC20262 0x4d38105a
#define ATA_PDC20263 0x0d38105a
#define ATA_PDC20265 0x0d30105a
#define ATA_PDC20267 0x4d30105a
#define ATA_PDC20268 0x4d68105a
--- ./dev/ata/ata-chipset.c.orig Sat Feb 3 22:09:56 2007
+++ ./dev/ata/ata-chipset.c Sat Feb 3 22:11:54 2007
@@ -2823,16 +2823,19 @@
{ ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
{ ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
{ ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
{ ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
{ ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
{ ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
{ ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
{ ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
+ { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
+ { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
+ { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
{ 0, 0, 0, 0, 0, 0}} ;
char buffer[64] ;
if (!(idx = ata_match_chip(dev, ids)))
return ENXIO;
sprintf(buffer, "nVidia %s %s controller",
idx->text, ata_mode2str(idx->max_dma));
--- ./dev/nve/if_nvereg.h.orig Sat Feb 3 22:02:39 2007
+++ ./dev/nve/if_nvereg.h Sat Feb 3 22:41:29 2007
@@ -43,16 +43,22 @@
#define NFORCE_MCPNET6_DEVICEID 0x00E6
#define NFORCE_MCPNET7_DEVICEID 0x00DF
#define NFORCE_MCPNET8_DEVICEID 0x0056
#define NFORCE_MCPNET9_DEVICEID 0x0057
#define NFORCE_MCPNET10_DEVICEID 0x0037
#define NFORCE_MCPNET11_DEVICEID 0x0038
#define NFORCE_MCPNET12_DEVICEID 0x0268
#define NFORCE_MCPNET13_DEVICEID 0x0269
+#define NFORCE_MCPNET14_DEVICEID 0x0372
+#define NFORCE_MCPNET15_DEVICEID 0x0373
+#define NFORCE_MCPNET16_DEVICEID 0x03e5
+#define NFORCE_MCPNET17_DEVICEID 0x03e6
+#define NFORCE_MCPNET18_DEVICEID 0x03ee
+#define NFORCE_MCPNET19_DEVICEID 0x03ef
#define NV_RID 0x10
#define TX_RING_SIZE 64
#define RX_RING_SIZE 64
#define NV_MAX_FRAGS 32 // match adapter.h:ADAPTER_WRITE_DATA.sElement[]
#define FCS_LEN 4
--- ./dev/nve/if_nve.c.orig Sat Feb 3 22:02:47 2007
+++ ./dev/nve/if_nve.c Sat Feb 3 23:22:56 2007
@@ -232,16 +232,24 @@
{NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID,
"NVIDIA nForce MCP10 Networking Adapter"},
{NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID,
"NVIDIA nForce MCP11 Networking Adapter"},
{NVIDIA_VENDORID, NFORCE_MCPNET12_DEVICEID,
"NVIDIA nForce MCP12 Networking Adapter"},
{NVIDIA_VENDORID, NFORCE_MCPNET13_DEVICEID,
"NVIDIA nForce MCP13 Networking Adapter"},
+ {NVIDIA_VENDORID, NFORCE_MCPNET16_DEVICEID,
+ "NVIDIA nForce MCP16 Networking Adapter"},
+ {NVIDIA_VENDORID, NFORCE_MCPNET17_DEVICEID,
+ "NVIDIA nForce MCP17 Networking Adapter"},
+ {NVIDIA_VENDORID, NFORCE_MCPNET18_DEVICEID,
+ "NVIDIA nForce MCP18 Networking Adapter"},
+ {NVIDIA_VENDORID, NFORCE_MCPNET19_DEVICEID,
+ "NVIDIA nForce MCP19 Networking Adapter"},
{0, 0, NULL}
};
/* DMA MEM map callback function to get data segment physical address */
static void
nve_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
{
if (error)
@@ -485,18 +493,28 @@
bzero(&sc->adapterdata, sizeof(sc->adapterdata));
sc->adapterdata.ulMediaIF = sc->media;
sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
/* MAC is loaded backwards into h/w reg */
sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
- for (i = 0; i < 6; i++) {
- eaddr[i] = sc->original_mac_addr[5 - i];
+ if (pci_get_device(dev) == NFORCE_MCPNET19_DEVICEID)
+ {
+ /* Already in the right order */
+ for (i = 0; i < 6; i++) {
+ eaddr[i] = sc->original_mac_addr[i];
+ }
+ }
+ else
+ {
+ for (i = 0; i < 6; i++) {
+ eaddr[i] = sc->original_mac_addr[5 - i];
+ }
}
sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
/* Display ethernet address ,... */
device_printf(dev, "Ethernet address %6D\n", eaddr, ":");
/* Allocate interface structures */
ifp = sc->ifp = if_alloc(IFT_ETHER);
--- ./pci/nfsmb.c.orig Sat Feb 3 22:08:10 2007
+++ ./pci/nfsmb.c Sat Feb 3 22:09:09 2007
@@ -32,16 +32,17 @@
#define NFSMB_DEVICEID_NF2_SMB 0x0064
#define NFSMB_DEVICEID_NF2_ULTRA_SMB 0x0084
#define NFSMB_DEVICEID_NF3_PRO150_SMB 0x00d4
#define NFSMB_DEVICEID_NF3_250GB_SMB 0x00e4
#define NFSMB_DEVICEID_NF4_SMB 0x0052
#define NFSMB_DEVICEID_NF4_04_SMB 0x0034
#define NFSMB_DEVICEID_NF4_51_SMB 0x0264
#define NFSMB_DEVICEID_NF4_55_SMB 0x0368
+#define NFSMB_DEVICEID_NF4_61_SMB 0x03eb
/* PCI Configuration space registers */
#define NF2PCI_SMBASE_1 PCIR_BAR(4)
#define NF2PCI_SMBASE_2 PCIR_BAR(5)
/*
* ACPI 3.0, Chapter 12, SMBus Host Controller Interface.
*/
@@ -118,16 +119,17 @@
case NFSMB_DEVICEID_NF2_SMB:
case NFSMB_DEVICEID_NF2_ULTRA_SMB:
case NFSMB_DEVICEID_NF3_PRO150_SMB:
case NFSMB_DEVICEID_NF3_250GB_SMB:
case NFSMB_DEVICEID_NF4_SMB:
case NFSMB_DEVICEID_NF4_04_SMB:
case NFSMB_DEVICEID_NF4_51_SMB:
case NFSMB_DEVICEID_NF4_55_SMB:
+ case NFSMB_DEVICEID_NF4_61_SMB:
device_set_desc(dev, "nForce2/3/4 MCP SMBus Controller");
return (BUS_PROBE_DEFAULT);
}
}
return (ENXIO);
}
@@ -200,16 +202,17 @@
case NFSMB_DEVICEID_NF2_SMB:
case NFSMB_DEVICEID_NF2_ULTRA_SMB:
case NFSMB_DEVICEID_NF3_PRO150_SMB:
case NFSMB_DEVICEID_NF3_250GB_SMB:
case NFSMB_DEVICEID_NF4_SMB:
case NFSMB_DEVICEID_NF4_04_SMB:
case NFSMB_DEVICEID_NF4_51_SMB:
case NFSMB_DEVICEID_NF4_55_SMB:
+ case NFSMB_DEVICEID_NF4_61_SMB:
/* Trying to add secondary device as slave */
nfsmb_sc->subdev = device_add_child(dev, "nfsmb", -1);
if (!nfsmb_sc->subdev)
return (EINVAL);
break;
default:
break;
}
>Release-Note:
>Audit-Trail:
>Unformatted:
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