From owner-svn-src-head@freebsd.org Tue Apr 18 10:39:15 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D7ADED44F6D; Tue, 18 Apr 2017 10:39:15 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B316015CB; Tue, 18 Apr 2017 10:39:15 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v3IAdE1K040245; Tue, 18 Apr 2017 10:39:14 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v3IAdElp040242; Tue, 18 Apr 2017 10:39:14 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201704181039.v3IAdElp040242@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Tue, 18 Apr 2017 10:39:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r317090 - in head/sys/arm/mv: . armada38x X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Apr 2017 10:39:15 -0000 Author: zbb Date: Tue Apr 18 10:39:14 2017 New Revision: 317090 URL: https://svnweb.freebsd.org/changeset/base/317090 Log: Optimize Armada38x low-level MBUS settings Add early init handler, which comprises various internal bus optimisations for Armada 38x SoC's. Magic values used due to undocumented registers. Submitted by: Marcin Wojtas , Arnaud Ysmal Obtained from: Semihalf, Stormshield Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10219 Modified: head/sys/arm/mv/armada38x/armada38x.c head/sys/arm/mv/mv_machdep.c head/sys/arm/mv/mvreg.h Modified: head/sys/arm/mv/armada38x/armada38x.c ============================================================================== --- head/sys/arm/mv/armada38x/armada38x.c Tue Apr 18 10:37:08 2017 (r317089) +++ head/sys/arm/mv/armada38x/armada38x.c Tue Apr 18 10:39:14 2017 (r317090) @@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$"); int armada38x_open_bootrom_win(void); int armada38x_scu_enable(void); int armada38x_win_set_iosync_barrier(void); +int armada38x_mbus_optimization(void); uint32_t get_tclk(void) @@ -115,6 +116,50 @@ armada38x_open_bootrom_win(void) } int +armada38x_mbus_optimization(void) +{ + bus_space_handle_t vaddr_iowind; + int rv; + + rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE, + MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind); + if (rv != 0) + return (rv); + + /* + * MBUS Units Priority Control Register - Prioritize XOR, + * PCIe and GbEs (ID=4,6,3,7,8) DRAM access + * GbE is High and others are Medium. + */ + bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180); + + /* + * Fabric Units Priority Control Register - + * Prioritize CPUs requests. + */ + bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A); + + /* + * MBUS Units Prefetch Control Register - + * Pre-fetch enable for all IO masters. + */ + bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF); + + /* + * Fabric Units Prefetch Control Register - + * Enable the CPUs Instruction and Data prefetch. + */ + bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303); + + bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN, + BUS_SPACE_BARRIER_WRITE); + + bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN); + + return (rv); +} + +int armada38x_scu_enable(void) { bus_space_handle_t vaddr_scu; Modified: head/sys/arm/mv/mv_machdep.c ============================================================================== --- head/sys/arm/mv/mv_machdep.c Tue Apr 18 10:37:08 2017 (r317089) +++ head/sys/arm/mv/mv_machdep.c Tue Apr 18 10:39:14 2017 (r317090) @@ -77,6 +77,7 @@ void armadaxp_l2_init(void); int armada38x_win_set_iosync_barrier(void); int armada38x_scu_enable(void); int armada38x_open_bootrom_win(void); +int armada38x_mbus_optimization(void); #endif #define MPP_PIN_MAX 68 @@ -259,6 +260,8 @@ platform_late_init(void) /* Set IO Sync Barrier bit for all Mbus devices */ if (armada38x_win_set_iosync_barrier() != 0) printf("WARNING: could not map CPU Subsystem registers\n"); + if (armada38x_mbus_optimization() != 0) + printf("WARNING: could not enable mbus optimization\n"); if (armada38x_scu_enable() != 0) printf("WARNING: could not enable SCU\n"); #ifdef SMP Modified: head/sys/arm/mv/mvreg.h ============================================================================== --- head/sys/arm/mv/mvreg.h Tue Apr 18 10:37:08 2017 (r317089) +++ head/sys/arm/mv/mvreg.h Tue Apr 18 10:39:14 2017 (r317090) @@ -447,4 +447,9 @@ #define CPU_RESET_ASSERT 0x1 #endif +#if defined(SOC_MV_ARMADA38X) +#define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420) +#define MV_MBUS_CTRL_REGS_LEN 0x10 +#endif + #endif /* _MVREG_H_ */