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From: Robert Watson <rwatson@FreeBSD.org>
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Subject: PERFORCE change 211453 for review
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http://p4web.freebsd.org/@@211453?ac=10

Change 211453 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/20 22:07:24

	Slight further reordering of locore -- no functional effect on
	CHERI, but on principle better to configure kernel memory cache
	coherency before starting to use CP2, rather than after.

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/locore.S#4 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/locore.S#4 (text+ko) ====

@@ -137,19 +137,27 @@
 	mtc0	t2, MIPS_COP_0_STATUS
 	COP0_SYNC
 
+	/* Make sure KSEG0 is cached */
+	li	t0, MIPS_CCA_CACHED
+	mtc0	t0, MIPS_COP_0_CONFIG
+	COP0_SYNC
+
 #if defined(CPU_CHERI)
 	/*
 	 * On CHERI MIPS, preserve the kernel's data segment context for use
 	 * in exception handlers.  $kcc will be preserved by the first eret.
 	 */
 	cmove	$c30, $c0		# Preserve $kdc
+
+	/*
+	 * Initialise saved user $c0 so we can later restore it.
+	 *
+	 * XXXRW: This will be removed once we more explicitly manage user
+	 * thread capabilities.
+	 */
+	cmove	$c27, $c0		#
 #endif
 
-	/* Make sure KSEG0 is cached */
-	li	t0, MIPS_CCA_CACHED
-	mtc0	t0, MIPS_COP_0_CONFIG
-	COP0_SYNC
-
 	/*xxximp
 	 * now that we pass a0...a3 to the platform_init routine, do we need
 	 * to stash this stuff here?