From owner-cvs-src@FreeBSD.ORG Tue Feb 1 18:13:35 2005 Return-Path: Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 292BB16A4D3 for ; Tue, 1 Feb 2005 18:13:32 +0000 (GMT) Received: from mail28.sea5.speakeasy.net (mail28.sea5.speakeasy.net [69.17.117.30]) by mx1.FreeBSD.org (Postfix) with ESMTP id 63B4B43D39 for ; Tue, 1 Feb 2005 18:13:31 +0000 (GMT) (envelope-from jhb@FreeBSD.org) Received: (qmail 14132 invoked from network); 1 Feb 2005 18:13:31 -0000 Received: from server.baldwin.cx ([216.27.160.63]) (envelope-sender )AES256-SHA encrypted SMTP for ; 1 Feb 2005 18:13:30 -0000 Received: from [10.50.40.202] (gw1.twc.weather.com [216.133.140.1]) (authenticated bits=0) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id j11IDLFH039638; Tue, 1 Feb 2005 13:13:26 -0500 (EST) (envelope-from jhb@FreeBSD.org) From: John Baldwin To: ticso@cicely.de Date: Tue, 1 Feb 2005 11:32:13 -0500 User-Agent: KMail/1.6.2 References: <200501312307.j0VN7gxm080740@repoman.freebsd.org> <200502010649.33768.jhb@FreeBSD.org> <20050201152803.GC31822@cicely12.cicely.de> In-Reply-To: <20050201152803.GC31822@cicely12.cicely.de> MIME-Version: 1.0 Content-Disposition: inline Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <200502011132.13288.jhb@FreeBSD.org> X-Spam-Status: No, score=-102.8 required=4.2 tests=ALL_TRUSTED, USER_IN_WHITELIST autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx cc: cvs-src@FreeBSD.org cc: Bernd Walter cc: src-committers@FreeBSD.org cc: cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/alpha/alpha machdep.c src/sys/alpha/include cpuconf.h src/sys/alpha/pci lca.c lcareg.h X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2005 18:13:36 -0000 On Tuesday 01 February 2005 10:28 am, Bernd Walter wrote: > On Tue, Feb 01, 2005 at 06:49:33AM -0500, John Baldwin wrote: > > On Monday 31 January 2005 06:07 pm, Bernd Walter wrote: > > > ticso 2005-01-31 23:07:42 UTC > > > > > > FreeBSD src repository > > > > > > Modified files: > > > sys/alpha/alpha machdep.c > > > sys/alpha/include cpuconf.h > > > sys/alpha/pci lca.c lcareg.h > > > Log: > > > add cpu_idle support for 21066A based lca systems > > > > > > Revision Changes Path > > > 1.229 +9 -1 src/sys/alpha/alpha/machdep.c > > > 1.14 +1 -0 src/sys/alpha/include/cpuconf.h > > > 1.21 +29 -0 src/sys/alpha/pci/lca.c > > > 1.4 +2 -0 src/sys/alpha/pci/lcareg.h > > > > What exactly are the writes to this register doing btw? Also, is there > > any reason we shouldn't just be using the PAL call that waits for the > > next interrupt instead? > > It reduces clock speed until the next interrupt on 21066A CPUs > and is a nop on plain 21066 CPUs. Hmm. > Would the PAL call work for SMP systems? Yes, though it says that the CPU counter can slow down while it is in the waiting state, so it seems that PAL is free to implement something just like what you did. > AFAIK no alpha CPU has native halt support so there is not much magic > that PAL can do for us. > What I've found out about this case is that alpha CPUs automaticaly > reduce power on unused parts and running just a tight loop, that works > without memory access, for a few microsecsonds might be more efficient > do do it ourself than calling PAL, which must be doing something > similar. > At least I think it is possible to reduce idle power consumption from > the current situation either way. Yes, right now we buzz loop with a memory access on each iteration, we could add a for loop that just decrements a counter to zero to the idle loop if desired. With preemption turned on we could have the idle process not check the run queues at all and just sit in a buzz loop. -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org