Date: Mon, 07 Feb 2011 14:06:11 -0600 From: Mark Tinguely <marktinguely@gmail.com> To: freebsd-arm@freebsd.org Subject: Re: Elimination of cpu_l2cache_* functions Message-ID: <4D5050B3.4070608@gmail.com> In-Reply-To: <857AA8D9-5C41-4D80-A3B5-0D29BE051014@mac.com> References: <857AA8D9-5C41-4D80-A3B5-0D29BE051014@mac.com>
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On 2/7/2011 12:43 PM, Marcel Moolenaar wrote:
> All,
>
> I've been reviewing the use of the cpu_l2cache_* functions and found
> that 1) they're missing from cpu_witch() and 2) they are always used
> in conjunction with either cpu_idcache_* or cpu_dcache_*.
>
> Since most CPU variants define them as null ops, isn't it better to
> incorporate the functionality of cpu_l2cache_* in cpu_idcache_* and
> cpu_dcache_* and eliminate them altogether?
>
> Any objections to me removing cpu_l2cache_* and therefore changing
> the semantics of cpu_idcache_* and cpu_dcahce_* to apply to all
> relevant cache levels?
>
> Thanks,
It was pointed out to me that the level two cache operation were removed
from the context switch on purpose, for performance reasons. I think
this exception is why we still have both a level one and level two cache
operation definitions.
I proposed the senerio that the Sheeva cluster IO filesystem corruption
problem is related to level two caches not being written back and
removed upon context switch. Assuming we want to keep the performance
gain by not performing the level two cache operations when we perform a
context switch, and since I believe that the Sheeva has PIPT level two
caches, I have a proposed fix to pmap_idcache_wdinv_range() that maps
the page to a local KVA and doing the appropriate level two cache
operation when needed.
---
In ARMv6 and ARMv7, the inner (level one) caches are PIPT, and all
these cache operations go away with the exception of the sync area of
the busdma routine.
--Mark Tinguely
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