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Date:      Thu, 8 Jan 2015 15:55:18 -0700
From:      Warner Losh <imp@bsdimp.com>
To:        Adrian Chadd <adrian@FreeBSD.org>
Cc:        "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org>
Subject:   Re: RFC: figuring out bus behaviour on these mips32r2 chips
Message-ID:  <B54C22FD-1EF2-4ABE-8ACF-002619ECA4EB@bsdimp.com>
In-Reply-To: <CAJ-Vmo=SY8q7fnycbjj_HVkLj0QdHymNftKXsmm1teussdMOrw@mail.gmail.com>
References:  <CAJ-Vmo=SY8q7fnycbjj_HVkLj0QdHymNftKXsmm1teussdMOrw@mail.gmail.com>

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> On Jan 7, 2015, at 6:03 PM, Adrian Chadd <adrian@FreeBSD.org> wrote:
>=20
> Hi,
>=20
> I found that the new QCA955x chip (and some of the QCA934x things in
> shipping products versus what I have on my desk at home) behave poorly
> unless I do ye olde "write to register; read from register to flush"
> paradigm.
>=20
> In this specific instance, it's the MDIO controller on each MAC - if I
> do a read-after-write to those registers, everything is peachy.
> Without it - and even with a call to wmb() - it still barfs.
>=20
> Now, I went digging through the mips code, and wmb() -> mips_sync() ->
> just a sync operation. It doesn't do any other kind of barrier.
>=20
> So - what's the mips32r2 spec require us to do for ensuring device IO
> has made it out to devices and we enforce ordering? Are we missing
> something in our mips_sync() implementation?

SYNC is supposed to be SYNC. An absolute barrier, but that may have =
weakened to being merely a strong ordering instruction such that all =
writes before it happen before all writes after it.

Warner


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