From owner-freebsd-questions  Fri Dec 15 14:53:50 1995
Return-Path: owner-questions
Received: (from root@localhost)
          by freefall.freebsd.org (8.7.3/8.7.3) id OAA24208
          for questions-outgoing; Fri, 15 Dec 1995 14:53:50 -0800 (PST)
Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211])
          by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id OAA24201
          for <questions@freebsd.org>; Fri, 15 Dec 1995 14:53:44 -0800 (PST)
Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id PAA04989; Fri, 15 Dec 1995 15:47:51 -0700
From: Terry Lambert <terry@lambert.org>
Message-Id: <199512152247.PAA04989@phaeton.artisoft.com>
Subject: Re: Upgrade - CPU, clock?
To: leisner@sdsp.mc.xerox.com (Marty Leisner)
Date: Fri, 15 Dec 1995 15:47:51 -0700 (MST)
Cc: gurney_j@efn.org, msmith@atrad.adelaide.edu.au, d_burr@ix.netcom.com,
        alan@trickler.uu.silcom.com, questions@freebsd.org
In-Reply-To: <9512151531.AA08003@gnu.mc.xerox.com> from "Marty Leisner" at Dec 15, 95 07:31:27 am
X-Mailer: ELM [version 2.4 PL24]
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Sender: owner-questions@freebsd.org
Precedence: bulk

> Can someone comment with some facts on how much difference L2 cache
> makes on DX4/100s?

		DX		DX2 (doubled)	DX4 (tripled)

L1		1 clock		1 clock		1 clock
L2		1 cycle		2 cycles	3 cycles
Memory		1 + I/O wait	2 + I/O wait	3 + I/O wait


A cycle is a memory bus cycle, which may be several clocks, depending
on interleaving, burst, etc.

Clearly, the higher the clock multiplier, the less use the L2 cache
and the more valuable the L1 cache.  I have a DX/50 that handily
outperforms a DX2/66, all other things being equal, because the L2
cache is accessed at 50 MHz instead of 33MHz, for instance.


					Terry Lambert
					terry@lambert.org
---
Any opinions in this posting are my own and not those of my present
or previous employers.