From owner-freebsd-arch@FreeBSD.ORG Sun Sep 14 09:18:12 2014 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 4B823D2A for ; Sun, 14 Sep 2014 09:18:12 +0000 (UTC) Received: from mail-la0-x229.google.com (mail-la0-x229.google.com [IPv6:2a00:1450:4010:c03::229]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C8CD0BA4 for ; Sun, 14 Sep 2014 09:18:11 +0000 (UTC) Received: by mail-la0-f41.google.com with SMTP id s18so3120661lam.0 for ; Sun, 14 Sep 2014 02:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=55h587AcfFIrXI2k/uBgPngp6V/oPphHreZKad6oAVQ=; b=ak8bOxWeYnmm2ffKP2g8pV+aJyRKpdupiq48QnrMbwlGaUWOqQqVtS9LXZdF9m6hIf vFTvr3PFUs6+ePYrlz8yVK9dXNx2hK6kujv+Gb0Q2896wa3p3Rq+B8S4DBiNZoRgkwxe SsPSD8hZ+j3FIycNlwd/y7d6qDFbnNHn/6qWezWutnMimETus4dPxUzQ5qxoKd4KXh8k t4c5zT/VKXMGxeqgcFxI/l2AHz29vH2xPsO/vfp5EJLI1HuyFODiM1AORhs0JdgpziOM sALRxyrLaMhua0TSZwe3BnWFuaLaRQ1wWqbInLKx2rJdqUvyVcNz4A3uoDuWLO2ujJFQ TcTg== MIME-Version: 1.0 X-Received: by 10.112.172.38 with SMTP id az6mr19276114lbc.53.1410686289750; Sun, 14 Sep 2014 02:18:09 -0700 (PDT) Received: by 10.25.42.83 with HTTP; Sun, 14 Sep 2014 02:18:09 -0700 (PDT) In-Reply-To: <20140914090033.GA2737@kib.kiev.ua> References: <20140913162059.GU2737@kib.kiev.ua> <20140914090033.GA2737@kib.kiev.ua> Date: Sun, 14 Sep 2014 11:18:09 +0200 Message-ID: Subject: Re: Intel MPX (Skylake ISA) support? From: Carsten Mattner To: Konstantin Belousov Content-Type: text/plain; charset=UTF-8 Cc: freebsd-arch@freebsd.org X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Sep 2014 09:18:12 -0000 On Sun, Sep 14, 2014 at 11:00 AM, Konstantin Belousov wrote: > On Sat, Sep 13, 2014 at 09:47:10PM +0200, Carsten Mattner wrote: >> On Sat, Sep 13, 2014 at 6:20 PM, Konstantin Belousov >> wrote: >> > On Sat, Sep 13, 2014 at 12:45:16PM +0200, Carsten Mattner wrote: >> >> Are there any plans to include the necessary (kernel, libc) support for >> >> Intel MPX (https://en.wikipedia.org/wiki/Intel_MPX)? >> > >> > I looked at this several times. The 319433 (Instructions Set Extensions >> > prog reference) even at the current revision 20 still seems to not provide >> > the complete documentation on the CPU side. E.g., could you point me at >> > the description of the save area for MPX ? It is required since usermode >> > bndcfg register can only be set by restoring from the XSAVE area. >> > >> > That said, I believe that most, if not all, of the needed kernel-side >> > support is already there by the generic XSAVE code. >> > >> > I never see any specification of runtime services expected by the code >> > generated by mpx-enabled gcc. >> >> Is https://lkml.org/lkml/2014/9/11/182 helpful? > > Not for me. I have zero interest in reverse-engineering Linux code > for core CPU functionality. Intel usually provides high-quality > documentation for the processors, and I hope that they will provide all > needed information together with the hardware release. > > Another significant missing piece is the lack of description of the > initial state and expectation of the runtime support in the ABI > document. The ABI draft 0.3 from July 17, 2013, specially edited for > MPX, only talks about argument passing conventions and dwarf, it seems. > > It is curious discussion about non-feasibility of implementing MPX > translation tables in usermode. Just for fun, I will try to do > something purely in usermode (when/if hardware will be available). More details I was able to find with links to hopefully descriptive documentation. IIUC developers have been using a well known Intel CPU simulator, but I'm in the dark there. gcc: http://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler glibc: https://sourceware.org/ml/libc-alpha/2014-03/msg00491.html https://sourceware.org/ml/libc-alpha/2014-03/msg00543.html https://sourceware.org/ml/libc-alpha/2014-03/msg00605.html