From owner-freebsd-mips@FreeBSD.ORG Sat Apr 6 22:21:47 2013 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 97FB21B1; Sat, 6 Apr 2013 22:21:47 +0000 (UTC) (envelope-from ray@freebsd.org) Received: from smtp.dlink.ua (smtp.dlink.ua [193.138.187.146]) by mx1.freebsd.org (Postfix) with ESMTP id 5247C36B; Sat, 6 Apr 2013 22:21:47 +0000 (UTC) Received: from rnote.ddteam.net (7-127-135-95.pool.ukrtel.net [95.135.127.7]) (Authenticated sender: ray) by smtp.dlink.ua (Postfix) with ESMTPSA id 3A76DC492D; Sun, 7 Apr 2013 01:13:14 +0300 (EEST) Date: Sun, 7 Apr 2013 01:13:07 +0300 From: Aleksandr Rybalko To: Adrian Chadd Subject: Re: [PATCH] MMC/SD SPI-mode driver Message-Id: <20130407011307.9a9a9d64.ray@freebsd.org> In-Reply-To: References: Organization: FreeBSD.ORG X-Mailer: Sylpheed 3.1.2 (GTK+ 2.24.5; amd64-portbld-freebsd9.0) X-Operating-System: FreeBSD Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: Dmytro , freebsd-mips@freebsd.org X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Apr 2013 22:21:47 -0000 On Fri, 5 Apr 2013 09:57:21 -0700 Adrian Chadd wrote: > On 5 April 2013 07:57, Patrick Kelsey wrote: > > > My understanding is that in the AR71xx (and possibly other related > > Atheros SoCs), the boot flash can be read through memory mapped > > access to a region starting at the reset address, as this is how > > booting from a serial flash is accomplished. In that scenario, the > > SPI controller > > Yes. > > > will be translating each read access into an SPI bus transaction > > that will produce the desired data from the flash. Since the > > hardware is performing the SPI signalling, you wouldn't have the > > CPU overhead of bitbanging each SPI bit out. Performance would > > still be limited by the value set in the SPI clock divider register > > (which controls the bit times on the wire) and the speed of the > > clock that runs the SPI unit itself. > > Yes. > > The problem here is that we're clocking out 8 bits via bit banging, > then we read the 8 bits from the Read register. > > So luckily we don't have to bitbang the reads and writes, but still. > > The SPI bus code looks pretty simplistic. There's no DELAY() entries > in the SPI code either. The only thing we haven't changed is the SPI > clock. > > Now, what Ray at zrouter did was to experiment with turning SPI > _flash_ reads into remap-and-memcpy. Look at > ath79_spi_do_read_flash_data(). It's a cute hack to improve read > performance, but you _absolutely need to know_ that it's a flash chip > and that the bus is locked for the duration of the read. You need the > SPI bus locked so you don't have someone come along during a transfer > loop and try to fiddle with the SPI registers. Yeah, found :) here it is http://zrouter.org/hg/FreeBSD/head/rev/a92b653f5b46 > > The other thing that has shown up is that they're doing some transfers > in more than 8 bits at a time? That may also help. > > Thanks, > > > Adrian > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to > "freebsd-mips-unsubscribe@freebsd.org" WBW -- Aleksandr Rybalko