From owner-freebsd-hardware Fri Jan 9 07:32:40 1998 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id HAA09817 for hardware-outgoing; Fri, 9 Jan 1998 07:32:40 -0800 (PST) (envelope-from owner-freebsd-hardware) Received: from ns.tar.com (ns.tar.com [204.95.187.2]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id HAA09807 for ; Fri, 9 Jan 1998 07:32:36 -0800 (PST) (envelope-from lists@tar.com) Received: from ppro.tar.com (ppro.tar.com [204.95.187.9]) by ns.tar.com (8.8.7/8.8.7) with SMTP id JAA17368; Fri, 9 Jan 1998 09:32:02 -0600 (CST) Message-Id: <199801091532.JAA17368@ns.tar.com> From: "Richard Seaman, Jr." To: "Greg Lehey" , "Mike Smith" Cc: "hardware@FreeBSD.ORG" Date: Fri, 09 Jan 98 09:32:01 -0500 Reply-To: "Richard Seaman, Jr." Priority: Normal X-Mailer: PMMail 1.92 For OS/2 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Subject: Re: LS-120, Riva 128, ASUS motherboard Sender: owner-freebsd-hardware@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk On Fri, 9 Jan 1998 19:40:06 +1030, Greg Lehey wrote: >Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. >Extract: > > The Intel 430TX PCIset (430TX) consists of the 82439TX System > Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator > (PIIX4). [...] The MTXC integrates the cache and main memory DRAM > control functions and provides bus control to transfers between the > CPU, cache, main memory, and the PCI Bus. The second level (L2) > cache controller supports a writeback cache policy for cache sizes > of 256 Kbytes and 512 Kbytes. > >I'm downloading the document, and will print it out, but this >certainly doesn't sound like Tom's Hardware Guide. >From http://www.intel.com/design/pcisets/datashts/29055901.pdf, page 46: Cacheability of the entire memory space in first level cache is supported, while only the lower 64 MB of main memory is cacheable in the second level cache.