From owner-freebsd-arm@freebsd.org Mon Dec 31 03:16:40 2018 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id EBE22141E91B for ; Mon, 31 Dec 2018 03:16:39 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound1a.eu.mailhop.org (outbound1a.eu.mailhop.org [52.58.109.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 394AD83B95 for ; Mon, 31 Dec 2018 03:16:38 +0000 (UTC) (envelope-from ian@freebsd.org) ARC-Seal: i=1; a=rsa-sha256; t=1546226192; cv=none; d=outbound.mailhop.org; s=arc-outbound20181012; b=rCaQmpnBE6QkhWfd1RNM9hHLQZdPLdvfPBtIvSnoorA+VROYNFBdKWTvdYupq4QEz3H3AVxw/9Ums GAfqHON5tMAd0NdBqmj9KuREp4xboMxmzqzWpRhLFlMp6bTXnP8YVyoW7ddSZARzijgmwYSg5FWS5p t75Al6zAcPfrMp2UfwWSMQ17X70cShRCZZ3R0uBfZU9fy5IV6dHXnc3adJXvbo5fZ1B5t+hvLmHyMg wv3vF/V7YSRBM+7FLDpDKLBIUqZIcy/Z9GSLZSL3eVlAUSKRMVNIAGjubzg2dnmnWP1U55+hCeM8Ga B4jgXvVhueX+HhR58J+jyCP8jKWJ/NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=outbound.mailhop.org; s=arc-outbound20181012; h=mime-version:content-type:references:in-reply-to:date:to:from:subject: message-id:dkim-signature:from; bh=9ksv/gO/3MlNiULA2z8nd9MuALu4r8ER3V3orvXyucI=; b=cPFm4Qg20mSoZpvPDih/RU0mxlDq3xuTpIn5pX6RxVRVq6fpWSU9u84SL90w9StQ/EudxVY1CsIKE WenUacN9El7e1CPZNlmNZnXLSWwcLuwQliLtTjy8Qi4P3YtSTYy1AU6roHEt63LGRZO4Xlr4gQQKwi kcfilEcnfpS7yl+IJ/vdaT4BgntusE87ak+rRIYylt+W+FHvfvzd+56edNIJ4tgG3UGxdtADWeaObX ncSmBdPZlXL5fNcmXk06q7BbLRsUQDzL83jnba3SExtffIUSPAli4zyVq5cofYFencgtZoOHUepX8U pCfGMmkruPtf/Ob7QXJMtMrxwhOhI2A== ARC-Authentication-Results: i=1; outbound2.eu.mailhop.org; spf=softfail smtp.mailfrom=freebsd.org smtp.remote-ip=67.177.211.60; dmarc=none header.from=freebsd.org; arc=none header.oldest-pass=0; DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outbound.mailhop.org; s=dkim-high; h=mime-version:content-type:references:in-reply-to:date:to:from:subject: message-id:from; bh=9ksv/gO/3MlNiULA2z8nd9MuALu4r8ER3V3orvXyucI=; b=Pk7u3geyqKSpyu3GJQG2SOW2MJp5gngznHozgCuRbIBYK4z0/7X/oWsYCrSSB2DuTFCFiB1mpAzdm p9qklWCLstmy4UAR0SJIdu6fMo8DzCb0alJtFBOcRo08decACBi20E81R583aHxsp/hjmdor+Hv53b OP4KdS7U0Zjt5PnWx/d+zX62iCQgcuvkaaZL7GwQWOdHfhPKH5hZiQoSK9fMpTrFqKrR4ngZzdk5aK Oov0YsM89dGyJTBkxLVyipEEeoLQBHMRBUSio4NxnAFe0lFS3HCPRLj7E/0381FNfAblFTFBmsUkQZ FthM8JgqPKWz696oAxh8FMtrkIecAUA== X-MHO-RoutePath: aGlwcGll X-MHO-User: 759bf020-0caa-11e9-a887-bd2f23b465e5 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 67.177.211.60 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [67.177.211.60]) by outbound2.eu.mailhop.org (Halon) with ESMTPSA id 759bf020-0caa-11e9-a887-bd2f23b465e5; Mon, 31 Dec 2018 03:16:30 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id wBV3GQDx030107; Sun, 30 Dec 2018 20:16:26 -0700 (MST) (envelope-from ian@freebsd.org) Message-ID: <1546226186.78877.97.camel@freebsd.org> Subject: Re: SPI start bit (9 bit) for BBB From: Ian Lepore To: SAITOU Toshihide , freebsd-arm@freebsd.org Date: Sun, 30 Dec 2018 20:16:26 -0700 In-Reply-To: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp> References: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp> Content-Type: multipart/mixed; boundary="=-Gjgpods0HzOcfsYoXlP1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 X-Rspamd-Queue-Id: 394AD83B95 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.98 / 15.00]; local_wl_from(0.00)[freebsd.org]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.98)[-0.981,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; ASN(0.00)[asn:16509, ipnet:52.58.0.0/15, country:US] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Dec 2018 03:16:40 -0000 --=-Gjgpods0HzOcfsYoXlP1 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 8bit On Mon, 2018-12-31 at 00:33 +0900, SAITOU Toshihide wrote: > In 3-line serial protcol, there is a type using additional 1-bit to > specify command or data.  The BBB can handle this, so I can use with > the following patch (unskillful and maybe side effects exist).  I > hope this will attract someones interest to implement this and also > SPI frequency and mode. > Since you are already set up for testing spi on BBB, could you please try the attached patch for handling bus speed and mode? If it works I'll get it committed. -- Ian --=-Gjgpods0HzOcfsYoXlP1 Content-Disposition: inline; filename="ti_spi_mode_freq.diff" Content-Type: text/x-patch; name="ti_spi_mode_freq.diff"; charset="ASCII" Content-Transfer-Encoding: 7bit Index: sys/arm/ti/ti_spi.c =================================================================== --- sys/arm/ti/ti_spi.c (revision 341650) +++ sys/arm/ti/ti_spi.c (working copy) @@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, stru { int err; struct ti_spi_softc *sc; - uint32_t reg, cs; + uint32_t clockhz, cs, mode, reg; sc = device_get_softc(dev); @@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, stru /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + spibus_get_clock(child, &clockhz); + spibus_get_mode(child, &mode); cs &= ~SPIBUS_CS_HIGH; @@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, stru return (EINVAL); } + if (mode > 3) + { + device_printf(dev, "Invalid mode %d requested by %s\n", mode, + device_get_nameunit(child)); + return (EINVAL); + } + TI_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ @@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, stru /* Disable FIFO for now. */ sc->sc_fifolvl = 1; - /* Use a safe clock - 500kHz. */ - ti_spi_set_clock(sc, sc->sc_cs, 500000); + /* Set the bus frequency. */ + ti_spi_set_clock(sc, sc->sc_cs, clockhz); /* Disable the FIFO. */ TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); @@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, stru MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; + reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */ TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); #if 0 --=-Gjgpods0HzOcfsYoXlP1--