From owner-svn-src-all@FreeBSD.ORG Tue Oct 25 23:17:54 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 33FA1106566B; Tue, 25 Oct 2011 23:17:54 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 2336B8FC12; Tue, 25 Oct 2011 23:17:54 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p9PNHs88021179; Tue, 25 Oct 2011 23:17:54 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p9PNHs8b021177; Tue, 25 Oct 2011 23:17:54 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201110252317.p9PNHs8b021177@svn.freebsd.org> From: Adrian Chadd Date: Tue, 25 Oct 2011 23:17:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r226762 - head/sys/dev/ath/ath_hal/ar5416 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Oct 2011 23:17:54 -0000 Author: adrian Date: Tue Oct 25 23:17:53 2011 New Revision: 226762 URL: http://svn.freebsd.org/changeset/base/226762 Log: Correct/complete a partially-disabled TX interrupt mitigation configuration. Although a previous commit disabled TX interrupt mitigation handling and configuration, the mask register bits weren't setup correctly. Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Tue Oct 25 23:14:40 2011 (r226761) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Tue Oct 25 23:17:53 2011 (r226762) @@ -358,12 +358,12 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMO */ OS_REG_WRITE(ah, AR_OBS, 8); -#ifdef AH_AR5416_INTERRUPT_MITIGATION /* * Disable the "general" TX/RX mitigation timers. */ OS_REG_WRITE(ah, AR_MIRT, 0); +#ifdef AH_AR5416_INTERRUPT_MITIGATION /* * This initialises the RX interrupt mitigation timers. * @@ -631,11 +631,11 @@ ar5416InitIMR(struct ath_hal *ah, HAL_OP | AR_IMR_BCNMISC; #ifdef AH_AR5416_INTERRUPT_MITIGATION - ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM - | AR_IMR_TXMINTR | AR_IMR_RXMINTR; + ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; #else - ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK; + ahp->ah_maskReg |= AR_IMR_RXOK; #endif + ahp->ah_maskReg |= AR_IMR_TXOK; if (opmode == HAL_M_HOSTAP) ahp->ah_maskReg |= AR_IMR_MIB;