From owner-svn-src-all@freebsd.org Sun Jun 26 18:43:44 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 43E00B8185F; Sun, 26 Jun 2016 18:43:44 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id F1349227D; Sun, 26 Jun 2016 18:43:43 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u5QIhheE012291; Sun, 26 Jun 2016 18:43:43 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u5QIhhnx012289; Sun, 26 Jun 2016 18:43:43 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201606261843.u5QIhhnx012289@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Sun, 26 Jun 2016 18:43:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r302214 - head/sys/powerpc/aim X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Jun 2016 18:43:44 -0000 Author: nwhitehorn Date: Sun Jun 26 18:43:42 2016 New Revision: 302214 URL: https://svnweb.freebsd.org/changeset/base/302214 Log: Enter 64-bit mode as early as possible in the 64-bit PowerPC boot sequence. Most of the effect of setting MSR[SF] is that the CPU will stop ignoring the high 32 bits of registers containing addresses in load/store instructions. As such, the kernel was setting it only when it began to need access to high memory. MSR[SF] also affects the operation of some conditional instructions, however, and so setting it at late times could subtly break code at very early times. This fixes use of the FDT mode in loader, and FDT boot more generally, on 64-bit PowerPC systems. Hardware provided by: IBM LTC Approved by: re (kib) Modified: head/sys/powerpc/aim/aim_machdep.c head/sys/powerpc/aim/locore64.S Modified: head/sys/powerpc/aim/aim_machdep.c ============================================================================== --- head/sys/powerpc/aim/aim_machdep.c Sun Jun 26 16:59:59 2016 (r302213) +++ head/sys/powerpc/aim/aim_machdep.c Sun Jun 26 18:43:42 2016 (r302214) @@ -179,17 +179,6 @@ aim_cpu_init(vm_offset_t toc) trap_offset = 0; cacheline_warn = 0; - #ifdef __powerpc64__ - /* - * Switch to 64-bit mode, if the bootloader didn't, before we start - * using memory beyond what the bootloader might have set up. - * Guaranteed not to cause an implicit branch since we either (a) - * started with a 32-bit bootloader below 4 GB or (b) were already in - * 64-bit mode, making this a no-op. - */ - mtmsrd(mfmsr() | PSL_SF); - #endif - /* Various very early CPU fix ups */ switch (mfpvr() >> 16) { /* Modified: head/sys/powerpc/aim/locore64.S ============================================================================== --- head/sys/powerpc/aim/locore64.S Sun Jun 26 16:59:59 2016 (r302213) +++ head/sys/powerpc/aim/locore64.S Sun Jun 26 18:43:42 2016 (r302214) @@ -76,6 +76,14 @@ btext: */ .text ASENTRY_NOPROF(__start) + /* Set 64-bit mode if not yet set before branching to C */ + mfmsr %r20 + li %r21,1 + insrdi %r20,%r21,1,0 + mtmsrd %r20 + isync + nop /* Make this block a multiple of 8 bytes */ + /* Set up the TOC pointer */ b 0f .align 3