Date: Thu, 16 May 1996 12:31:53 +0200 (MET DST) From: J Wunsch <j@uriah.heep.sax.de> To: rgrimes@GndRsh.aac.dev.com (Rodney W. Grimes) Cc: jgreco@brasil.moneng.mei.com, davidg@Root.COM, mmead@Glock.COM, joerg_wunsch@uriah.heep.sax.de, blh@nol.net, hackers@freebsd.org, hardware@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605161031.MAA01458@uriah.heep.sax.de> In-Reply-To: <199605151704.KAA04912@GndRsh.aac.dev.com> from "Rodney W. Grimes" at "May 15, 96 10:04:45 am"
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As Rodney W. Grimes wrote: > > > ECC has single bit error correction and 2 bit error detection. Better than > > > parity no matter how you slice it. > > Only if you have memory that is failing or you need extreamly reliable > operation (good memory should have a single bit error rate of something > like 1 in 10 years). I think most of the memory problems we've been observing lately are not related to the RAM itself, but rather to other hardware problems (timing, EMC problems). Remember all the reports about ``strange sig 10/11's'' or the Winbloze ``general protection failure'' mess where you never know whether it's actually hardware or rather an o/s failure. -- cheers, J"org joerg_wunsch@uriah.heep.sax.de -- http://www.sax.de/~joerg/ -- NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-)
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