Date: Fri, 13 Aug 1999 12:12:14 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: alc@cs.rice.edu (Alan Cox) Cc: cvs-committers@freebsd.org, cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/vm vm_page.h Message-ID: <199908131912.MAA01913@gndrsh.aac.dev.com> In-Reply-To: <19990813140128.C27982@cs.rice.edu> from Alan Cox at "Aug 13, 1999 02:01:28 pm"
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> On Fri, Aug 13, 1999 at 07:58:43AM -0700, Rodney W. Grimes wrote: > > > alc 1999/08/12 14:16:55 PDT > > > > > > Modified files: > > > sys/vm vm_page.h > > > Log: > > > Make the default page coloring parameters match a (non-Xeon) Pentium II/III. > > > > > > This setting is also acceptable for Celerons and Pentium Pros > > > with less than 1MB L2 caches. > > > > > > Note: PQ_L2_SIZE is a misnomer. The correct number of colors is > > > a function of the cache's degree of associativity as well as its size. > > > > Yea... has anyone looked at creating the right color scheme for the > > AMD K6-III 4-way L2 cache? If access to the correct hardware is an issue > > I should be able to help with that. > > > > In theory, a Celeron needs only 8 colors, a Pentium Pro with 256KB cache > needs only 16 colors, and a K6-III is complicated. :-) > > The answer for a K6-III depends on whether the coloring wants > or needs to take into account the direct-map L3 cache. If it doesn't, > then 16 colors should suffice. If it does, then 128 (512KB L3) or > 256 (1MB L3) are necessary. And there are even a few rare boards out there now with 2MB L3, and that should be the limit if I recall the MVP3 data sheets correctly. It might be interesting to run with 16 colors and the L3 cache turned off... humm... and maybe a few permutations with and without coloring with and without L3. I suspect an L3 direct mapped cache with an L2 4 set associative in front of it to be a waste of silicon :-) > Do you know if the inclusion property holds between the on-chip L2 > and the motherboard-level L3? I don't, but just how would that work given that they are direct vs set associative, which means that L3 could not hold certain areas that could be in L2 due to collision in the direct map. This should also hold true for the L1 vs L2 on Pentium and above processors. > As a rule, using a few too many colors is okay, but using too few > colors is no good. :-) -- Rod Grimes - KD7CAX - (RWG25) rgrimes@gndrsh.dnsmgr.net To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message
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