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Date:      Tue, 14 Jan 2025 22:37:28 +0000
From:      bugzilla-noreply@freebsd.org
To:        usb@FreeBSD.org
Subject:   [Bug 284042] FTDI: UART breaks JTAG
Message-ID:  <bug-284042-19105-uK8mdZgYCj@https.bugs.freebsd.org/bugzilla/>
In-Reply-To: <bug-284042-19105@https.bugs.freebsd.org/bugzilla/>
References:  <bug-284042-19105@https.bugs.freebsd.org/bugzilla/>

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D284042

--- Comment #7 from Tomasz "CeDeROM" CEDRO <tomek@cedro.info> ---
Very cool that modern uftdi can disable JATG port not to be grabbed by ucom=
 it
was not there back then. From my initial report it seems it was working as =
ucom
then jtag then ucom then jtag.. so probably a bug in uftdi / ucom :-( Accor=
ding
to FT2232H datasheet it is possible to configure two channels independently=
 so
one works as UART and the other one works as MPSSE in theory they should not
disturb each other.

https://ftdichip.com/wp-content/uploads/2024/09/DS_FT2232H.pdf


Regarding USB-Serial-JTAG the ESP32-C3 and ESP-C6 (RISC-V CPU) indeed has s=
ome
minimalistic implementation. But if you look at ESP32-S3 TRM Chapter 33 Page
1247:

> The CPU JTAG signals can be routed to the USB Serial/JTAG Controller or e=
xternal GPIO  pads using eFuses
> and when the user program has started, software control as well. At that =
time, the JTAG signals from the USB
> Serial/JTAG can also be routed to the GPIO matrix. This allows debugging =
a secondary SoC via JTAG using the
> ESP32-S3 USB Serial/JTAG Controller.

It would not be RISC-V CPU but the probe can be built that way utilizing ES=
P's
JTAG Command Processor. What is more both channels use CDC-ACM so it should=
 be
also possible to expose this simple serial transport over BLE or WIFI. Wish=
 I
had time to play around with it. Unfortunately I could not find anyone
interested in funding this kind of research. Maybe you can make it happen :=
-)

https://www.espressif.com/sites/default/files/documentation/esp32-s3_techni=
cal_reference_manual_en.pdf

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