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From: Oleksandr Tymoshenko <gonzo@FreeBSD.org>
Date: Tue, 27 Nov 2012 06:39:33 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r243602 - head/sys/arm/arm
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Author: gonzo
Date: Tue Nov 27 06:39:32 2012
New Revision: 243602
URL: http://svnweb.freebsd.org/changeset/base/243602

Log:
  Do not enable data cache until later in kernel init. Stale bits in
  cache might cause erroneus behavior on early stage.
  
  Submitted by:	Ian Lepore
  Tested on:	Atmel, Marvell, and Eyxnos

Modified:
  head/sys/arm/arm/locore.S

Modified: head/sys/arm/arm/locore.S
==============================================================================
--- head/sys/arm/arm/locore.S	Tue Nov 27 06:35:26 2012	(r243601)
+++ head/sys/arm/arm/locore.S	Tue Nov 27 06:39:32 2012	(r243602)
@@ -181,7 +181,7 @@ Lunmapped:
 #if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
 	orr	r0, r0, #CPU_CONTROL_V6_EXTPAGE
 #endif
-	orr	r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
+	orr	r0, r0, #(CPU_CONTROL_MMU_ENABLE)
 	mcr	p15, 0, r0, c1, c0, 0
 	nop
 	nop