From owner-svn-src-head@FreeBSD.ORG Sun Mar 1 07:00:35 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 83BA0EE3; Sun, 1 Mar 2015 07:00:35 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 554303F2; Sun, 1 Mar 2015 07:00:35 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t2170ZGk071617; Sun, 1 Mar 2015 07:00:35 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t2170ZOV071616; Sun, 1 Mar 2015 07:00:35 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201503010700.t2170ZOV071616@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sun, 1 Mar 2015 07:00:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279480 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Mar 2015 07:00:35 -0000 Author: adrian Date: Sun Mar 1 07:00:34 2015 New Revision: 279480 URL: https://svnweb.freebsd.org/changeset/base/279480 Log: Add very initial QCA955x awareness to the GPIO code. There's a lot more to come - the QCA955x has a bunch more GPIO MUX configuration, reminiscent of what the ARM chips let you do - but it'll have to come later. Modified: head/sys/mips/atheros/ar71xx_gpio.c Modified: head/sys/mips/atheros/ar71xx_gpio.c ============================================================================== --- head/sys/mips/atheros/ar71xx_gpio.c Sun Mar 1 06:59:32 2015 (r279479) +++ head/sys/mips/atheros/ar71xx_gpio.c Sun Mar 1 07:00:34 2015 (r279480) @@ -50,9 +50,10 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include -#include +#include #include "gpio_if.h" @@ -96,7 +97,9 @@ ar71xx_gpio_function_enable(struct ar71x { if (ar71xx_soc == AR71XX_SOC_AR9341 || ar71xx_soc == AR71XX_SOC_AR9342 || - ar71xx_soc == AR71XX_SOC_AR9344) + ar71xx_soc == AR71XX_SOC_AR9344 || + ar71xx_soc == AR71XX_SOC_QCA9556 || + ar71xx_soc == AR71XX_SOC_QCA9558) GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask); else GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask); @@ -107,7 +110,9 @@ ar71xx_gpio_function_disable(struct ar71 { if (ar71xx_soc == AR71XX_SOC_AR9341 || ar71xx_soc == AR71XX_SOC_AR9342 || - ar71xx_soc == AR71XX_SOC_AR9344) + ar71xx_soc == AR71XX_SOC_AR9344 || + ar71xx_soc == AR71XX_SOC_QCA9556 || + ar71xx_soc == AR71XX_SOC_QCA9558) GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask); else GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask); @@ -169,6 +174,9 @@ ar71xx_gpio_pin_max(device_t dev, int *m case AR71XX_SOC_AR9342: case AR71XX_SOC_AR9344: *maxpin = AR934X_GPIO_COUNT - 1; + case AR71XX_SOC_QCA9556: + case AR71XX_SOC_QCA9558: + *maxpin = QCA955X_GPIO_COUNT - 1; break; default: *maxpin = AR71XX_GPIO_PINS - 1;