From owner-cvs-src-old@FreeBSD.ORG Thu Jan 21 02:21:45 2010 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 50C521065768 for ; Thu, 21 Jan 2010 02:21:45 +0000 (UTC) (envelope-from neel@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 3F9A48FC14 for ; Thu, 21 Jan 2010 02:21:45 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id o0L2LjMZ062069 for ; Thu, 21 Jan 2010 02:21:45 GMT (envelope-from neel@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id o0L2LjqF062068 for cvs-src-old@freebsd.org; Thu, 21 Jan 2010 02:21:45 GMT (envelope-from neel@repoman.freebsd.org) Message-Id: <201001210221.o0L2LjqF062068@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to neel@repoman.freebsd.org using -f From: Neel Natu Date: Thu, 21 Jan 2010 02:21:31 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/mips/mips exception.S X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2010 02:21:45 -0000 neel 2010-01-21 02:21:31 UTC FreeBSD src repository Modified files: sys/mips/mips exception.S Log: SVN rev 202732 on 2010-01-21 02:21:31Z by neel Get rid of redundant setting of interrupt enable bit when restoring the status register from the PCB. Remove a couple of misleading comments while I am here. The comments are misleading because they imply that interrupts will be enabled after the status register is restored from the PCB. This is not the case because the processor is at the exception level (SR_EXL is set). Approved by: imp (mentor) Revision Changes Path 1.4 +1 -13 src/sys/mips/mips/exception.S