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Date: Fri, 9 Jun 2023 19:58:04 GMT
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To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org,
dev-commits-src-branches@FreeBSD.org
From: Mitchell Horne <mhorne@FreeBSD.org>
Subject: git: 4f845152b19b - stable/13 - hwpmc: trim obsolete Intel CPU and class defs
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The branch stable/13 has been updated by mhorne:
URL: https://cgit.FreeBSD.org/src/commit/?id=4f845152b19b154f4df65886c60f23c105d0c6fd
commit 4f845152b19b154f4df65886c60f23c105d0c6fd
Author: Mitchell Horne <mhorne@FreeBSD.org>
AuthorDate: 2023-05-05 21:57:38 +0000
Commit: Mitchell Horne <mhorne@FreeBSD.org>
CommitDate: 2023-06-09 18:14:58 +0000
hwpmc: trim obsolete Intel CPU and class defs
No functional change.
Reviewed by: jkoshy
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D39904
(cherry picked from commit ca43b2ae3ef2ed86b0df36296464d7830b61b944)
---
sys/dev/hwpmc/hwpmc_intel.c | 2 +-
sys/i386/include/pmc_mdep.h | 4 ----
sys/sys/pmc.h | 10 ----------
3 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 894f9c07b622..c51e74f34516 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -99,7 +99,7 @@ pmc_intel_initialize(void)
family, model, stepping);
switch (cpu_id & 0xF00) {
- case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
+ case 0x600:
switch (model) {
case 0xE:
cputype = PMC_CPU_INTEL_CORE;
diff --git a/sys/i386/include/pmc_mdep.h b/sys/i386/include/pmc_mdep.h
index a868ce11c3ca..3d498e006a36 100644
--- a/sys/i386/include/pmc_mdep.h
+++ b/sys/i386/include/pmc_mdep.h
@@ -45,10 +45,6 @@ struct pmc_mdep;
* TSC The timestamp counter
* K7 AMD Athlon XP/MP and other 32 bit processors.
* K8 AMD Athlon64 and Opteron PMCs in 32 bit mode.
- * PIV Intel P4/HTT and P4/EMT64
- * PPRO Intel Pentium Pro, Pentium-II, Pentium-III, Celeron and
- * Pentium-M processors
- * PENTIUM Intel Pentium MMX.
* IAP Intel Core/Core2/Atom programmable PMCs.
* IAF Intel fixed-function PMCs.
* UCP Intel Uncore programmable PMCs.
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
index 91ce5d2bd71f..4b645c771484 100644
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -84,13 +84,6 @@ extern char pmc_cpuid[PMC_CPUID_LEN];
#define __PMC_CPUS() \
__PMC_CPU(AMD_K7, 0x00, "AMD K7") \
__PMC_CPU(AMD_K8, 0x01, "AMD K8") \
- __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
- __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
- __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
- __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
- __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
- __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
- __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
__PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
__PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
__PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
@@ -153,9 +146,6 @@ enum pmc_cputype {
__PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
__PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
__PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
- __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \
- __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \
- __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \
__PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
__PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
__PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \