Date: Thu, 26 Jan 2023 19:48:04 GMT From: John Baldwin <jhb@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 1f1b3763610a - stable/13 - bhyve: Implement MSR_MISC_FEATURES_ENABLES Message-ID: <202301261948.30QJm4gP007475@gitrepo.freebsd.org>
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The branch stable/13 has been updated by jhb: URL: https://cgit.FreeBSD.org/src/commit/?id=1f1b3763610a2e9f58ab50e811f279d8db164e3d commit 1f1b3763610a2e9f58ab50e811f279d8db164e3d Author: Warner Losh <imp@FreeBSD.org> AuthorDate: 2022-10-27 17:32:18 +0000 Commit: John Baldwin <jhb@FreeBSD.org> CommitDate: 2023-01-26 19:43:20 +0000 bhyve: Implement MSR_MISC_FEATURES_ENABLES Linux reads MISC_FEATURES_ENABLES to manage the CPUID faulting feature (undocumented in the Intel SDM, but documented in 323850-004 (Intel Virtualization Technology FlexMigration Application Note). Since bhyve doesn't emulate this feature, we always return 0. Neither does bhyve support the MONITOR/MWAIT fault bit also in this MSR (which is documented in the sdm), so always return 0. Sponsored by: Netflix Reviewed by: jhb Differential Revision: https://reviews.freebsd.org/D36602 (cherry picked from commit 1d21f64149224000d74e0c850686e85aefd25ef9) --- sys/x86/include/specialreg.h | 1 + usr.sbin/bhyve/xmsr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index bc3fd2e563a1..395338b4a4b4 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -564,6 +564,7 @@ #define MSR_BBL_CR_CTL3 0x11e #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_MCU_OPT_CTRL 0x123 +#define MSR_MISC_FEATURE_ENABLES 0x140 #define MSR_SYSENTER_CS_MSR 0x174 #define MSR_SYSENTER_ESP_MSR 0x175 #define MSR_SYSENTER_EIP_MSR 0x176 diff --git a/usr.sbin/bhyve/xmsr.c b/usr.sbin/bhyve/xmsr.c index 563743dd05b4..5f735152e92c 100644 --- a/usr.sbin/bhyve/xmsr.c +++ b/usr.sbin/bhyve/xmsr.c @@ -117,6 +117,7 @@ emulate_rdmsr(struct vmctx *ctx __unused, int vcpu __unused, uint32_t num, case MSR_PP0_ENERGY_STATUS: case MSR_PP1_ENERGY_STATUS: case MSR_DRAM_ENERGY_STATUS: + case MSR_MISC_FEATURE_ENABLES: *val = 0; break; case MSR_RAPL_POWER_UNIT:
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