From owner-svn-src-all@freebsd.org Mon Dec 14 18:02:38 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 29424A1407C; Mon, 14 Dec 2015 18:02:38 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0A9431A68; Mon, 14 Dec 2015 18:02:38 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from ralph.baldwin.cx (c-73-231-226-104.hsd1.ca.comcast.net [73.231.226.104]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id E365AB93E; Mon, 14 Dec 2015 13:02:36 -0500 (EST) From: John Baldwin To: Andrew Turner Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r292214 - head/sys/arm64/arm64 Date: Mon, 14 Dec 2015 10:00:10 -0800 Message-ID: <2514466.bN9s7sMlTf@ralph.baldwin.cx> User-Agent: KMail/4.14.3 (FreeBSD/10.2-STABLE; KDE/4.14.3; amd64; ; ) In-Reply-To: <201512141607.tBEG7KpJ041632@repo.freebsd.org> References: <201512141607.tBEG7KpJ041632@repo.freebsd.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Mon, 14 Dec 2015 13:02:37 -0500 (EST) X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Dec 2015 18:02:38 -0000 On Monday, December 14, 2015 04:07:20 PM Andrew Turner wrote: > Author: andrew > Date: Mon Dec 14 16:07:20 2015 > New Revision: 292214 > URL: https://svnweb.freebsd.org/changeset/base/292214 > > Log: > Add support for MSI interrupts to the gicv2m controller. The allocation > is still quite simplistic, it just increments a counter to use the next > interrupt. > > Obtained from: ABT Systems Ltd > Sponsored by: SoftIron Inc Does this work for a count > 1? With MSI (but not MSI-X) when you have a count > 1, you typically need an aligned, contiguous block of vectors. In particular, for MSI you can only request a power of 2 number of messages. The low N bits (where N == log base 2 of 'count') of the resulting 'data' register value (from PCIB_MAP_MSI()) must be zero for the first message in the block. When the PCI function wants to send a message, it stores the message index (i.e. which MSI message) in the low N bits). On x86 the low 8 bits of the data message are the IDT vector, so this means that MSI message blocks require an aligned, contiguous block of IDT vectors on the destination CPU. MSI-X avoids this need by providing separate address/data register pairs for each message, so each message can use an arbitrary vector. You do seem to use a contiguous block of vectors, but it's not clear they are aligned? -- John Baldwin