From owner-freebsd-isp Wed Feb 26 05:06:33 1997 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.5/8.8.5) id FAA05938 for isp-outgoing; Wed, 26 Feb 1997 05:06:33 -0800 (PST) Received: from zwei.siemens.at (zwei.siemens.at [193.81.246.12]) by freefall.freebsd.org (8.8.5/8.8.5) with ESMTP id FAA05918; Wed, 26 Feb 1997 05:06:22 -0800 (PST) Received: from sol1.gud.siemens.co.at (root@[10.1.143.100]) by zwei.siemens.at (8.7.5/8.7.3) with SMTP id OAA12605; Wed, 26 Feb 1997 14:07:44 +0100 (MET) Received: from ws2301.gud.siemens.co.at by sol1.gud.siemens.co.at with smtp (Smail3.1.28.1 #7 for ) id m0vzj38-0001zDC; Wed, 26 Feb 97 14:05 MET Received: by ws2301.gud.siemens.co.at (1.37.109.16/1.37) id AA083142096; Wed, 26 Feb 1997 14:01:36 +0100 From: "Hr.Ladavac" Message-Id: <199702261301.AA083142096@ws2301.gud.siemens.co.at> Subject: Re: [H] Optimal computer for FreeBSD To: vince@mail.MCESTATE.COM (Vincent Poy) Date: Wed, 26 Feb 1997 14:01:36 +0100 (MEZ) Cc: michaelv@MindBender.serv.net, tom@sdf.com, sergey@extech.msk.su, freebsd-isp@freebsd.org, freebsd-hackers@freebsd.org In-Reply-To: from "Vincent Poy" at Feb 26, 97 04:14:41 am X-Mailer: ELM [version 2.4 PL24 ME8a] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-isp@freebsd.org X-Loop: FreeBSD.org Precedence: bulk E-mail message from Vincent Poy contained: > On Tue, 25 Feb 1997, Michael L. VanLoon -- HeadCandy.com wrote: > > > > Always use parity RAM on servers, especially if you are buying > > >everything from scratch. > > > EDO doesn't give you much of a improvement if your motherboard supports > > >pipeline-burst-cache. > > > > My guess is that it doesn't, since the cache is built into the CPU... > > :-) > > Actually, from what Rodney Grimes had told me, the cache built > into the CPU is the L1 (Level 1) cache while the L2 cache is the cache on > the motherboard, with Pipeline Burst Caching, it will give like the same > improvement EDO ram will give with a non-PBC Cache but if used in > conjunction with PBC, the increase isn't that big to make much of a > difference. With the slight exception of PPro processors where both L1 and L2 caches reside in the same package, albeit on two separate pieces of sillicon... /Marino > > > Cheers, > Vince - vince@MCESTATE.COM - vince@GAIANET.NET ________ __ ____ > Unix Networking Operations - FreeBSD-Real Unix for Free / / / / | / |[__ ] > GaiaNet Corporation - M & C Estate / / / / | / | __] ] > Beverly Hills, California USA 90210 / / / / / |/ / | __] ] > HongKong Stars/Gravis UltraSound Mailing Lists Admin /_/_/_/_/|___/|_|[____] > > >