Date: Sat, 30 Mar 1996 02:11:04 +0900 From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp> To: hackers@freebsd.org Subject: M1sc support Message-ID: <199603291711.CAA00276@marble.eps.nagoya-u.ac.jp>
next in thread | raw e-mail | index | archive | help
I would like to contribute M1sc (Cyrix 5x86) support code for
FreeBSD-current.
Motivation:
Though Cyrix says 5x86 is not an upgrade product, Cyrix KK sells it as
an upgrade product only in Japan. Therefore, many people use the 5x86
on the main board which does not support the 5x86 in Japan. Such 5x86
users want to enable 5x86 features, especially write-back cache on
their FreeBSD boxes.
How to Use:
The 5x86 features can be enabled/disabled by the following kernel
configuration options:
options "DISABLE_5x86_LSSER"
Disable load store serialize.
options "RSTK_EN"
Enable return stack.
options "LOOP_EN"
Enable loop pre-fetch buffer.
options "SUSP_HLT"
Enter suspend mode when hlt is executed.
options "CYRIX_CACHE_WORKS"
Execute wbinvd instruction before DMA transfer.
MB which doesn't support M1sc needs this options.
options "FASTER_5X86_FPU"
Enable fast FPU exception reporting.
When this option is enabled, exception from FPU cannot be
detected.
Note: Write-back cache and branch prediction are always enabled.
---------- BEGIN ----------
diff -c -r sys.old/i386/i386/locore.s sys/i386/i386/locore.s
*** sys.old/i386/i386/locore.s Fri Mar 29 23:47:21 1996
--- sys/i386/i386/locore.s Fri Mar 29 23:49:03 1996
***************
*** 348,353 ****
--- 348,365 ----
jnz 1f
movl $CPU_486,_cpu-KERNBASE
+
+ /* check for Cyrix CPU */
+ movl $0x5555,%eax
+ xorl %edx,%edx
+ movl $2,%ecx
+ clc
+ divl %ecx
+ jc 3f # Intel chip
+
+ movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
+ movw $0x0078,_cpu_vendor-KERNBASE+4
+
/* check for Cyrix 486DLC -- based on check routine */
/* documented in "Cx486SLC/e SMM Programmer's Guide" */
xorw %dx,%dx
***************
*** 363,373 ****
andw $0x08d5,%cx
cmpw %ax,%cx
! jnz 3f # if flags changed, Intel chip
movl $CPU_486DLC,_cpu-KERNBASE # set CPU value for Cyrix
- movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string
- movw $0x0078,_cpu_vendor-KERNBASE+4
#ifndef CYRIX_CACHE_WORKS
/* Disable caching of the ISA hole only. */
--- 375,383 ----
andw $0x08d5,%cx
cmpw %ax,%cx
! jnz cy5x86 # must not be 486DLC
movl $CPU_486DLC,_cpu-KERNBASE # set CPU value for Cyrix
#ifndef CYRIX_CACHE_WORKS
/* Disable caching of the ISA hole only. */
***************
*** 425,430 ****
--- 435,516 ----
movl %eax,%cr0
invd
#endif /* CYRIX_CACHE_WORKS */
+ jmp 3f
+
+ cy5x86:
+ /* Cyrix 5x86 (M1sc) */
+ movl $CPU_M1SC,_cpu-KERNBASE # set value for M1sc
+
+ /* enable 5x86 feature */
+ cli
+ mov %cr0,%eax
+ orl $0x40000000,%eax # disable cache
+ movl %eax,%cr0
+
+ wbinvd # flush buffer
+
+ movb $0xc3,%al
+ outb %al,$0x22
+ inb $0x23,%al
+
+ movb $0x0c1,%al # CCR1
+ outb %al,$0x22
+ movb $0x00,%al
+ outb %al,$0x23
+ movb $0x0c2,%al # CCR2
+ outb %al,$0x22
+ #ifdef SUSP_HLT
+ movb $0x0a,%al # USE_WBAK, SUSP_HLT
+ #else
+ movb $0x02,%al # USE_WBAK
+ #endif
+ outb %al,$0x23 # Interface Pins
+ movb $0xc3,%al # CCR3
+ outb %al,$0x22 #
+ movb $0x10,%al # MAPEN0 (to access CCR4)
+ outb %al,$0x23
+ movb $0x0e8,%al # CCR4
+ outb %al,$0x22
+ #ifdef FASTER_5X86_FPU
+ movb $0x38,%al # DTE_EN,MEM_BYP,no clock delay
+ # UNDOCUMENTED OPTION (20H)
+ #else
+ movb $0x18,%al # DTE_EN,MEM_BYP,no clock delay
+ #endif
+ outb %al,$0x23
+ movb $0x020,%al # PCR0
+ outb %al,$0x22
+ #ifdef RSTK_EN
+ #define RSTK_EN_BIT 1
+ #else
+ #define RSTK_EN_BIT 0
+ #endif
+ #ifdef LOOP_EN
+ #define LOOP_EN_BIT 4
+ #else
+ #define LOOP_EN_BIT 0
+ #endif
+ #ifdef DISABLE_5X86_LSSER
+ movb $(0x02 | RSTK_EN_BIT | LOOP_EN_BIT) ,%al # BTB_EN
+ #else
+ movb $(0x82 | RSTK_EN_BIT | LOOP_EN_BIT),%al # BTB_EN,LSSER
+ #endif
+ outb %al,$0x23
+ movb $0x0c3,%al # CCR3
+ outb %al,$0x22
+ movb $0x00,%al
+ outb %al,$0x23
+ movb $0x80,%al # dummy
+ outb %al,$0x22
+ inb $0x23,%al
+
+ movl %cr0,%ebx
+ andl $0x0bfffffff,%ebx # enable cache
+ orl $0x020000000,%ebx # write back mode
+ movl %ebx,%cr0 # go!
+
+ sti
+
jmp 3f
1: /* Use the `cpuid' instruction. */
diff -c -r sys.old/i386/i386/machdep.c sys/i386/i386/machdep.c
*** sys.old/i386/i386/machdep.c Fri Mar 29 23:47:21 1996
--- sys/i386/i386/machdep.c Fri Mar 29 23:51:26 1996
***************
*** 484,489 ****
--- 484,490 ----
{ "Pentium", CPUCLASS_586 }, /* CPU_586 */
{ "Cy486DLC", CPUCLASS_486 }, /* CPU_486DLC */
{ "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
+ { "M1sc", CPUCLASS_486 }, /* CPU_M1SC */
};
static void
diff -c -r sys.old/i386/include/cputypes.h sys/i386/include/cputypes.h
*** sys.old/i386/include/cputypes.h Fri Mar 29 23:47:21 1996
--- sys/i386/include/cputypes.h Fri Mar 29 23:56:34 1996
***************
*** 51,56 ****
#define CPU_486 4 /* Intel 80486DX */
#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's TM) */
#define CPU_486DLC 6 /* Cyrix 486DLC */
! #define CPU_686 7 /* Pentium Pro */
#endif /* _MACHINE_CPUTYPES_H_ */
--- 51,57 ----
#define CPU_486 4 /* Intel 80486DX */
#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's TM) */
#define CPU_486DLC 6 /* Cyrix 486DLC */
! #define CPU_686 7 /* Pentium Pro */
! #define CPU_M1SC 8 /* Cyrix 5x86 */
#endif /* _MACHINE_CPUTYPES_H_ */
diff -c -r sys.old/i386/isa/isa.c sys/i386/isa/isa.c
*** sys.old/i386/isa/isa.c Fri Mar 29 23:47:21 1996
--- sys/i386/isa/isa.c Fri Mar 29 23:54:42 1996
***************
*** 653,658 ****
--- 653,663 ----
/* translate to physical */
phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
+ #ifdef CYRIX_CACHE_WORKS
+ if (cpu == CPU_M1SC)
+ asm("wbinvd");
+ #endif
+
if ((chan & 4) == 0) {
/*
* Program one of DMA channels 0..3. These are
---------- END ----------
----
KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ., Nagoya, 464-01, Japan
Voice: +81-52-789-2529 Fax: +81-52-789-3033
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199603291711.CAA00276>