Date: Thu, 16 Jul 2015 05:09:59 +0000 From: "wma_semihalf.com (Wojciech Macek)" <phabric-noreply@FreeBSD.org> To: freebsd-arm@freebsd.org Subject: [Differential] [Request, 5 lines] D3106: Fix possible coherency issues between PEs related to I-cache Message-ID: <differential-rev-PHID-DREV-7jvrfu7n4cao4babkh3e-req@FreeBSD.org>
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wma_semihalf.com created this revision.
wma_semihalf.com added reviewers: andrew, emaste, zbb.
wma_semihalf.com added a subscriber: freebsd-arm-list.
wma_semihalf.com set the repository for this revision to rS FreeBSD src repository.
Herald added subscribers: emaste, andrew, imp.
REVISION SUMMARY
Basing on B.2.3.4:
Synchronization and coherency issues between data and
instruction accesses.
To ensure that modified instructions are visible to all PEs
in a shareability domain one need to perform following sequence:
1. Clean D-cache
2. Ensure the visibility of data cleaned from cache
3. Invalidate I-cache
4. Ensure completion
5. In SMP system PE must issue isb to ensure execution of the
modified instructions
REPOSITORY
rS FreeBSD src repository
REVISION DETAIL
https://reviews.freebsd.org/D3106
AFFECTED FILES
sys/arm64/arm64/cpufunc_asm.S
CHANGE DETAILS
diff --git a/sys/arm64/arm64/cpufunc_asm.S b/sys/arm64/arm64/cpufunc_asm.S
--- a/sys/arm64/arm64/cpufunc_asm.S
+++ b/sys/arm64/arm64/cpufunc_asm.S
@@ -61,17 +61,18 @@
add x1, x1, x2 /* Add these to the size */
bic x0, x0, x4 /* Clear the low bit of the address */
1:
+ dc \dcop, x0
+ dsb ish
.if \ic != 0
ic \icop, x0
+ dsb ish
.endif
- dc \dcop, x0
add x0, x0, x3 /* Move to the next line */
subs x1, x1, x3 /* Reduce the size */
b.hi 1b /* Check if we are done */
.if \ic != 0
isb
.endif
- dsb ish
ret
.endm
EMAIL PREFERENCES
https://reviews.freebsd.org/settings/panel/emailpreferences/
To: wma_semihalf.com, andrew, emaste, zbb
Cc: imp, andrew, freebsd-arm-list, emaste
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