From owner-freebsd-hardware Fri Jan 9 07:50:48 1998 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id HAA12021 for hardware-outgoing; Fri, 9 Jan 1998 07:50:48 -0800 (PST) (envelope-from owner-freebsd-hardware) Received: from silvia.HIP.Berkeley.EDU (ala-ca34-45.ix.netcom.com [207.93.143.173]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id HAA11992 for ; Fri, 9 Jan 1998 07:50:41 -0800 (PST) (envelope-from asami@vader.cs.berkeley.edu) Received: (from asami@localhost) by silvia.HIP.Berkeley.EDU (8.8.8/8.6.9) id HAA00879; Fri, 9 Jan 1998 07:24:37 -0800 (PST) Date: Fri, 9 Jan 1998 07:24:37 -0800 (PST) Message-Id: <199801091524.HAA00879@silvia.HIP.Berkeley.EDU> To: grog@lemis.com CC: mike@smith.net.au, hardware@FreeBSD.ORG In-reply-to: <19980109194006.42229@lemis.com> (message from Greg Lehey on Fri, 9 Jan 1998 19:40:06 +1030) Subject: Re: LS-120, Riva 128, ASUS motherboard From: asami@cs.berkeley.edu (Satoshi Asami) Sender: owner-freebsd-hardware@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk * Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. : * I'm downloading the document, and will print it out, but this * certainly doesn't sound like Tom's Hardware Guide. Spare the trees. It's right there on the first page of the spec sheet (in .pdf): : @ Integrated L2 Cache Controller --- 64-MB DRAM Cacheability : Satoshi