From owner-svn-src-head@FreeBSD.ORG Sun May 2 01:51:11 2010 Return-Path: Delivered-To: svn-src-head@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 8A787106566B; Sun, 2 May 2010 01:51:11 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 4AABD8FC18; Sun, 2 May 2010 01:51:11 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o421li6n040425; Sat, 1 May 2010 19:47:45 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 01 May 2010 19:47:58 -0600 (MDT) Message-Id: <20100501.194758.49280345204940330.imp@bsdimp.com> To: doconnor@gsoft.com.au From: "M. Warner Losh" In-Reply-To: <9624CC6A-EEB1-4492-9E62-7ACD0BF6F39C@gsoft.com.au> References: <201005011636.o41GaFsK084343@svn.freebsd.org> <9624CC6A-EEB1-4492-9E62-7ACD0BF6F39C@gsoft.com.au> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org Subject: Re: svn commit: r207472 - in head/sys: conf dev/ath/ath_hal/ar5212 X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 May 2010 01:51:11 -0000 In message: <9624CC6A-EEB1-4492-9E62-7ACD0BF6F39C@gsoft.com.au> "Daniel O'Connor" writes: : : On 02/05/2010, at 2:06 AM, Warner Losh wrote: : > Unfortunately, this condition is impossible to detect at runtime : > without MIPS specific ifdefs. Rather than cast an overly-broad net : > like Linux/OpenWRT dues (which enables this workaround all the time on : > MIPS32 platforms), we put this option in the kernel for just the : > affected machines. Sam didn't like this aspect of the patch when he : > reviewed it, and I'd love to hear sane proposals on how to fix it :) : : Could you do TUNABLE_INT in the MIPS code and TUNABLE_INT_FETCH in ath_hal? How is that better than a kernel option? The only place this would ever happen is atheros AR71xx SoC. It isn't like some of the Atheros 71xx SoCs would have it and some wouldn't. And besides, kenv has to be compiled into the kernel on MIPS these days... The only thing close to an idea I've had is to add: __weak int ath_needs_dma_war() { return 0; } and have this in the mips: int needs_ath_dma_war = 0; __weak int ath_needs_dma_war() { return needs_ath_dma_war; } and set it to 1 in the AR71xx CPU initialization. But that seemed kind of lame... Warner