From nobody Fri Jun 9 19:58:05 2023 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QdBhY62dVz4cKW2; Fri, 9 Jun 2023 19:58:05 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QdBhY5cMCz4JPZ; Fri, 9 Jun 2023 19:58:05 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1686340685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=X9zofmrSSvisZJnuTmPYEPyXAtkKyjBuIO10fFSgvtw=; b=nxTCwR8ZNkT4ORgc7ynHkeCj8DLXN2plJvSKMFvZ3BIVoQnj5g6C+HocYvnPRKEGsrSap8 /O997b8e/SoPMu/gLpowJfQEmHbBtPIAOs5I7IxWOFeEzSir8XTcfOsQZuB7Wi3gflC1Yj Al23dbuRU+A7iErAgILM8G2cJOyHawsST9367NAAckIKz/4j5aGgqNX9pUA4ndsjieGah+ jIW5rlGnZMuR1d1FlXav3cAfxrQqrTTJiZfe3Zd71LRutVWmN8gigyIkBFCLouUgKE1rhE ma026u9pqq+mviT4stszs9PyBKYLPKhVARYUG7KaFIG1YnXW+5+E1p+tVVisLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1686340685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=X9zofmrSSvisZJnuTmPYEPyXAtkKyjBuIO10fFSgvtw=; b=i5hH5i6Aj6SoaKnvGXtHC50OMEVUSWZJgoi5bopS1don+KM85gi+YBeWvMrYQkc7fqr5Qc /ZuA83WhQ+V/dFt+HjD1OvNKRxiuZADbcTxXGNzbhtHmB2/8Cuq5/Jib/GLUr2BJzaElvt QZ9qnCSPf9U81hFeZiW4GUBZ+runPsS7NZe2qiDP5wUrC0Nj3gVpJWYY8zQVyRqSxQzGjp N3lAkTfhLqVUDqVFwdnaApDjsUKJ/bBKU2CxboD5XkAq/Xaiic3FR32vFRJb0KLvoMuaC8 tFgwK2cR/2RrdkBVjY9pHL/QnIICLlf+uT9b3l1q0Lo8DDfu8/Z+PpdlO23a4Q== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1686340685; a=rsa-sha256; cv=none; b=U0fw36JVkU9gVQaCI/92A/y/1lmd5xPrmve9VeYh7xU9wdtGPNglt2JNOUAluy/00LCw4U hHfv4VBv6/S6blnlwl6+D8CnjaxcZxWUklUHAKwgXxw8/rzIByNp+hWVyBxwvCT/SeJZNh L8j0V+xDy2yW7My/GEGgAZZw3ZiKxKfJ8hb7lZuGcOqB7P+7RuyuR7kK9dgLty/vNeI5iV UZ3k9SDgqzJHsTDjXKCU3K4yqpYfXVvlwt8WqbPSZ2ClmhiE6Dapa/d2c1CL9zCaike3V4 nmjxoQUxMKnAX8SUQG5QsWGdPzXTdh2cVWkJsOc6frUmSj1Vwd3RokE44R5eQQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QdBhY4Td1znmr; Fri, 9 Jun 2023 19:58:05 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 359Jw54Y072116; Fri, 9 Jun 2023 19:58:05 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 359Jw5kg072115; Fri, 9 Jun 2023 19:58:05 GMT (envelope-from git) Date: Fri, 9 Jun 2023 19:58:05 GMT Message-Id: <202306091958.359Jw5kg072115@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Mitchell Horne Subject: git: fd9f6074dc71 - stable/13 - hwpmc: formatting of CPU and class lists List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-branches@freebsd.org X-BeenThere: dev-commits-src-branches@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: fd9f6074dc71e2e18c7091909d67a257bfd2528c Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=fd9f6074dc71e2e18c7091909d67a257bfd2528c commit fd9f6074dc71e2e18c7091909d67a257bfd2528c Author: Mitchell Horne AuthorDate: 2023-05-05 21:58:13 +0000 Commit: Mitchell Horne CommitDate: 2023-06-09 18:14:58 +0000 hwpmc: formatting of CPU and class lists The end result is much more legible in both cases. Reviewed by: jkoshy MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39906 (cherry picked from commit 7253dc57a0b400ff745a43017928304ff8dcf33f) --- sys/sys/pmc.h | 136 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 67 insertions(+), 69 deletions(-) diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 4b645c771484..8f817658fe55 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -80,54 +80,53 @@ extern char pmc_cpuid[PMC_CPUID_LEN]; * and numbered sparsely in order to minimize changes to the ABI involved * when new CPUs are added. */ - -#define __PMC_CPUS() \ - __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ - __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ - __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ - __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ - __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ - __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ - __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ - __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ - __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ - __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ - __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ - __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ - __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ - __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ - __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ - __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ - __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ - __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ - __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ - __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ - __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ - __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ - __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ - __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ - __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ - __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ - __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ - __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ - __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ - __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ - __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ - __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ - __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ - __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ - __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ - __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ - __PMC_CPU(GENERIC, 0x400, "Generic") \ - __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ - __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ - __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ - __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ - __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ - __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ - __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ - __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ - __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") +#define __PMC_CPUS() \ + __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ + __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ + __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ + __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ + __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ + __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ + __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ + __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ + __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ + __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ + __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ + __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ + __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ + __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ + __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ + __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ + __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ + __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ + __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ + __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ + __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ + __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ + __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ + __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ + __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ + __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ + __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ + __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ + __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ + __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ + __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ + __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ + __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ + __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ + __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ + __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ + __PMC_CPU(GENERIC, 0x400, "Generic") \ + __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ + __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ + __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ + __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ + __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ + __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ + __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ + __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ + __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") enum pmc_cputype { #undef __PMC_CPU @@ -141,27 +140,26 @@ enum pmc_cputype { /* * Classes of PMCs */ - -#define __PMC_CLASSES() \ - __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ - __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ - __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ - __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ - __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ - __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ - __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ - __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ - __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ - __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ - __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ - __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ - __PMC_CLASS(SOFT, 0x0F, "Software events") \ - __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ - __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ - __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ - __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ - __PMC_CLASS(BERI, 0x14, "MIPS BERI") \ - __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") +#define __PMC_CLASSES() \ + __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ + __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ + __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ + __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ + __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ + __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ + __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ + __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ + __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ + __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ + __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ + __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ + __PMC_CLASS(SOFT, 0x0F, "Software events") \ + __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ + __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ + __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ + __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ + __PMC_CLASS(BERI, 0x14, "MIPS BERI") \ + __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ enum pmc_class { #undef __PMC_CLASS