From owner-p4-projects@FreeBSD.ORG Thu Mar 3 21:26:00 2005 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id E222B16A4D0; Thu, 3 Mar 2005 21:25:59 +0000 (GMT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A190616A4CE; Thu, 3 Mar 2005 21:25:59 +0000 (GMT) Received: from cs.rice.edu (cs.rice.edu [128.42.1.30]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6EA6643D4C; Thu, 3 Mar 2005 21:25:59 +0000 (GMT) (envelope-from alc@cs.rice.edu) Received: from localhost (calypso.cs.rice.edu [128.42.1.127]) by cs.rice.edu (Postfix) with ESMTP id 133BF4A9BB; Thu, 3 Mar 2005 15:25:58 -0600 (CST) Received: from cs.rice.edu ([128.42.1.30]) by localhost (calypso.cs.rice.edu [128.42.1.127]) (amavisd-new, port 10024) with LMTP id 08699-01-81; Thu, 3 Mar 2005 15:25:58 -0600 (CST) Received: by cs.rice.edu (Postfix, from userid 19572) id 732D74A9B1; Thu, 3 Mar 2005 15:25:58 -0600 (CST) Date: Thu, 3 Mar 2005 15:25:58 -0600 From: Alan Cox To: John Baldwin Message-ID: <20050303212558.GA16936@cs.rice.edu> References: <200503032104.j23L4Pjw010114@repoman.freebsd.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200503032104.j23L4Pjw010114@repoman.freebsd.org> User-Agent: Mutt/1.4.2i X-Virus-Scanned: by amavis-2.2.1 at cs.rice.edu cc: Perforce Change Reviews cc: Alan Cox Subject: Re: PERFORCE change 72450 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Mar 2005 21:26:00 -0000 On Thu, Mar 03, 2005 at 09:04:25PM +0000, John Baldwin wrote: > http://perforce.freebsd.org/chv.cgi?CH=72450 > > Change 72450 by jhb@jhb_slimer on 2005/03/03 21:03:35 > > Clobber memory for cas{x,}a() inlines. > > Suggested by: alc > > Affected files ... > > .. //depot/projects/smpng/sys/sparc64/include/cpufunc.h#20 edit > > Differences ... > > ==== //depot/projects/smpng/sys/sparc64/include/cpufunc.h#20 (text+ko) ==== > > @@ -63,14 +63,14 @@ > #define casa(rs1, rs2, rd, asi) ({ \ > u_int __rd = (uint32_t)(rd); \ > __asm __volatile("casa [%1] %2, %3, %0" \ > - : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \ > + : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2) : "memory");\ > __rd; \ > }) > > #define casxa(rs1, rs2, rd, asi) ({ \ > u_long __rd = (uint64_t)(rd); \ > __asm __volatile("casxa [%1] %2, %3, %0" \ > - : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \ > + : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2) : "memory");\ > __rd; \ > }) > The other, arguably "more correct", option is to declare the memory location referenced by rs1 as an input and output operand, like so from i386: (I say "more correct" because the true operand here is the memory location referenced by rs1 not rs1 the register.) static __inline pt_entry_t pte_load_store(pt_entry_t *ptep, pt_entry_t pte) { pt_entry_t r; __asm __volatile( "xchgl %0,%1" : "=m" (*ptep), "=r" (r) : "1" (pte), "m" (*ptep)); return (r); } (Note: this example does not use "+m" as an output constraint because Tor convinced me a few months ago that the gcc docs prohibit that: "+" is only to be used with registers.) Returning to the sparc, I'm not sure what the right constraint is for cas{x,}a's rs1. I don't believe that "m" is appropriate because this particular instruction doesn't allow the destination to be a register plus an constant offset. Perhaps, "V"? That said, we should add a "memory" clobber to the sparc64 atomic ops that include a memory barrier, particularly, the acquires. Regards, Alan