Date: Sun, 20 May 2012 22:09:31 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 211454 for review Message-ID: <201205202209.q4KM9VvE057251@skunkworks.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://p4web.freebsd.org/@@211454?ac=10 Change 211454 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/20 22:08:44 When creating and maintaining kernel and user contexts, force coprocessor 2 to be enabled. In a few places comment on the paucity of this approach. In the future we will want to conditionally manage CHERI CP2 context as is done for CP1 and Octeon CP2 support, reducing context switch costs when the features aren't in active use. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/pm_machdep.c#2 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/vm_machdep.c#3 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/pm_machdep.c#2 (text+ko) ==== @@ -523,6 +523,9 @@ td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; #endif +#if defined(CPU_CHERI) + td->td_frame->sr |= MIPS_SR_COP_2_BIT; +#endif /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/vm_machdep.c#3 (text+ko) ==== @@ -165,7 +165,12 @@ td2->td_md.md_saved_intr = MIPS_SR_INT_IE; td2->td_md.md_spinlock_count = 1; #ifdef CPU_CHERI - /* XXXRW: CP2 state management here. */ + /* + * XXXRW: Ensure capability coprocessor is enabled for both kernel and + * userspace in child. + */ + td2->td_frame->sr |= MIPS_SR_COP_2_BIT; + pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT; #endif #ifdef CPU_CNMIPS if (td1->td_md.md_flags & MDTD_COP2USED) { @@ -411,6 +416,13 @@ pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() & (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK); +#ifdef CPU_CHERI + /* + * XXXRW: Interesting that we just set pcb_context here and not also + * the trap frame. + */ + pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT; +#endif #ifdef CPU_CNMIPS pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; @@ -470,6 +482,9 @@ /* * Keep interrupt mask + * + * XXXRW: I'm a bit puzzled by the code below and feel that even if it + * works, it can't really be right. */ td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE | (mips_rd_status() & MIPS_SR_INT_MASK); @@ -478,6 +493,9 @@ #elif defined(__mips_n64) td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif +#ifdef CPU_CHERI + tf->sr |= MIPS_SR_COP_2_BIT; +#endif #ifdef CPU_CNMIPS tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201205202209.q4KM9VvE057251>