From owner-p4-projects@FreeBSD.ORG Wed Jan 10 09:41:55 2007 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 3F00616A562; Wed, 10 Jan 2007 09:41:55 +0000 (UTC) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 0416F16A55A for ; Wed, 10 Jan 2007 09:41:54 +0000 (UTC) (envelope-from ticso@cicely12.cicely.de) Received: from raven.bwct.de (raven.bwct.de [85.159.14.73]) by mx1.freebsd.org (Postfix) with ESMTP id 3A5C913C448 for ; Wed, 10 Jan 2007 09:41:54 +0000 (UTC) (envelope-from ticso@cicely12.cicely.de) Received: from cicely5.cicely.de ([10.1.1.7]) by raven.bwct.de (8.13.4/8.13.4) with ESMTP id l0A9N0Qb062506; Wed, 10 Jan 2007 10:23:00 +0100 (CET) (envelope-from ticso@cicely12.cicely.de) Received: from cicely12.cicely.de (cicely12.cicely.de [10.1.1.14]) by cicely5.cicely.de (8.13.4/8.13.4) with ESMTP id l0A9MqOb022548 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 10 Jan 2007 10:22:53 +0100 (CET) (envelope-from ticso@cicely12.cicely.de) Received: from cicely12.cicely.de (localhost [127.0.0.1]) by cicely12.cicely.de (8.13.4/8.13.3) with ESMTP id l0A9MqwZ087123; Wed, 10 Jan 2007 10:22:52 +0100 (CET) (envelope-from ticso@cicely12.cicely.de) Received: (from ticso@localhost) by cicely12.cicely.de (8.13.4/8.13.3/Submit) id l0A9Mqij087122; Wed, 10 Jan 2007 10:22:52 +0100 (CET) (envelope-from ticso) Date: Wed, 10 Jan 2007 10:22:52 +0100 From: Bernd Walter To: Warner Losh Message-ID: <20070110092251.GG80390@cicely12.cicely.de> References: <200701100703.l0A734xi068010@repoman.freebsd.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200701100703.l0A734xi068010@repoman.freebsd.org> X-Operating-System: FreeBSD cicely12.cicely.de 5.4-STABLE alpha User-Agent: Mutt/1.5.9i X-Spam-Status: No, score=-4.4 required=5.0 tests=ALL_TRUSTED=-1.8, BAYES_00=-2.599 autolearn=ham version=3.1.7 X-Spam-Checker-Version: SpamAssassin 3.1.7 (2006-10-05) on cicely12.cicely.de Cc: Perforce Change Reviews Subject: Re: PERFORCE change 112701 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: ticso@cicely.de List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jan 2007 09:41:55 -0000 On Wed, Jan 10, 2007 at 07:03:04AM +0000, Warner Losh wrote: > http://perforce.freebsd.org/chv.cgi?CH=112701 > > Change 112701 by imp@imp_lighthouse on 2007/01/10 07:02:04 > > Add a comment about why we need to do the dance we do with enabling > the PDC, along with a simplified version of the code. > > Affected files ... > > .. //depot/projects/arm/src/sys/arm/at91/at91_mci.c#30 edit > > Differences ... > > ==== //depot/projects/arm/src/sys/arm/at91/at91_mci.c#30 (text+ko) ==== > > @@ -402,16 +402,27 @@ > } > } > // printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg); > + /* > + * For Reads, we need to enable the DMA buffer before we send > + * the command. For writes, alas, it has to be enabled after > + * we send the command. If enabled after the CMDR write for > + * reads, fast SD parts could win the race that's present and > + * the result would be corrupted data because the ENDRX bit > + * would be set, but the dma wouldn't have started yet. When > + * that interrupt returned, we'd enable DMA. We'd then get a > + * RXBUFF interrupt and then a CMDRDY interrupt. We'd process > + * things int he ISR. But since the DMA started after we got > + * the ENDRX and RXBUFF interrupts, when we got the CMDRDY > + * interrupt the data would still be in flight, leading to > + * corruption. This race was 'hard' to trigger for slow parts, > + * but easy to trigger for faster ones. > + */ > WR4(sc, MCI_ARGR, cmd->arg); > - if (cmdr & MCI_CMDR_TRCMD_START) { > - if (cmdr & MCI_CMDR_TRDIR) { > - WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN); > - WR4(sc, MCI_CMDR, cmdr); > - } else { > - WR4(sc, MCI_CMDR, cmdr); > - WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN); > - } > - } > + if ((cmdr & MCI_CMDR_TRCMD_START) && (cmdr & MCI_CMDR_TRDIR)) > + WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN); > + WR4(sc, MCI_CMDR, cmdr); > + if ((cmdr & MCI_CMDR_TRCMD_START) && !(cmdr & MCI_CMDR_TRDIR)) > + WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN); > WR4(sc, MCI_IER, MCI_SR_ERROR | ier); > } > This moves MCI_CMDR writing out of the (cmdr & MCI_CMDR_TRCMD_START) check. -- B.Walter http://www.bwct.de http://www.fizon.de bernd@bwct.de info@bwct.de support@fizon.de