Date: Wed, 6 May 2009 04:32:11 GMT From: Arnar Mar Sig <antab@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 161648 for review Message-ID: <200905060432.n464WBId081760@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=161648 Change 161648 by antab@antab_farm on 2009/05/06 04:31:38 Copy more of at91 usart driver, there are some nazty hacks in there to have sysdev and dbg port on the same uart and not race with interrupts and PDC. Affected files ... .. //depot/projects/avr32/src/sys/avr32/include/reg_pdc.h#1 add .. //depot/projects/avr32/src/sys/dev/uart/uart_atmel.h#2 edit .. //depot/projects/avr32/src/sys/dev/uart/uart_bus_atmel.c#4 edit .. //depot/projects/avr32/src/sys/dev/uart/uart_dev_atmel.c#6 edit Differences ... ==== //depot/projects/avr32/src/sys/dev/uart/uart_atmel.h#2 (text+ko) ==== @@ -1,6 +1,5 @@ /*- - * Copyright (c) 2008 Arnar Mar Sig - * All rights reserved. + * Copyright (c) 2005 Olivier Houchard. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -11,316 +10,122 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. */ +/* $FreeBSD: src/sys/arm/at91/at91_usartreg.h,v 1.3 2008/11/25 00:13:26 imp Exp $ */ + #ifndef _DEV_UART_ATMEL_H_ #define _DEV_UART_ATMEL_H_ extern struct uart_class uart_atmel_class; -struct uart_atmel_softc { +#define USART_CR 0x00 /* Control register */ +#define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */ +#define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */ +#define USART_CR_RXEN (1UL << 4) /* Receiver Enable */ +#define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */ +#define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */ +#define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */ +#define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */ +#define USART_CR_STTBRK (1UL << 9) /* Start Break */ +#define USART_CR_STPBRK (1UL << 10) /* Stop Break */ +#define USART_CR_STTTO (1UL << 11) /* Start Time-out */ +#define USART_CR_SENDA (1UL << 12) /* Send Address */ +#define USART_CR_RSTIT (1UL << 13) /* Reset Iterations */ +#define USART_CR_RSTNACK (1UL << 14) /* Reset Non Acknowledge */ +#define USART_CR_RETTO (1UL << 15) /* Rearm Time-out */ +#define USART_CR_DTREN (1UL << 16) /* Data Terminal ready Enable */ +#define USART_CR_DTRDIS (1UL << 17) /* Data Terminal ready Disable */ +#define USART_CR_RTSEN (1UL << 18) /* Request to Send enable */ +#define USART_CR_RTSDIS (1UL << 19) /* Request to Send Disable */ -}; +#define USART_MR 0x04 /* Mode register */ +#define USART_MR_MODE_NORMAL 0 /* Normal/Async/3-wire rs-232 */ +#define USART_MR_MODE_RS485 1 /* RS485 */ +#define USART_MR_MODE_HWFLOW 2 /* Hardware flow control/handshake */ +#define USART_MR_MODE_MODEM 3 /* Full modem protocol */ +#define USART_MR_MODE_ISO7816T0 4 /* ISO7816 T=0 */ +#define USART_MR_MODE_ISO7816T1 6 /* ISO7816 T=1 */ +#define USART_MR_MODE_IRDA 8 /* IrDA mode */ +#define USART_MR_USCLKS_MCK (0U << 4) /* use MCK for baudclock */ +#define USART_MR_USCLKS_MCKDIV (1U << 4) /* use MCK/DIV for baudclock */ +#define USART_MR_USCLKS_SCK (3U << 4) /* use SCK (ext) for baudclock */ +#define USART_MR_CHRL_5BITS (0U << 6) +#define USART_MR_CHRL_6BITS (1U << 6) +#define USART_MR_CHRL_7BITS (2U << 6) +#define USART_MR_CHRL_8BITS (3U << 6) +#define USART_MR_SYNC (1U << 8) /* 1 -> sync 0 -> async */ +#define USART_MR_PAR_EVEN (0U << 9) +#define USART_MR_PAR_ODD (1U << 9) +#define USART_MR_PAR_SPACE (2U << 9) +#define USART_MR_PAR_MARK (3U << 9) +#define USART_MR_PAR_NONE (4U << 9) +#define USART_MR_PAR_MULTIDROP (6U << 9) +#define USART_MR_NBSTOP_1 (0U << 12) +#define USART_MR_NBSTOP_1_5 (1U << 12) +#define USART_MR_NBSTOP_2 (2U << 12) +#define USART_MR_CHMODE_NORMAL (0U << 14) +#define USART_MR_CHMODE_ECHO (1U << 14) +#define USART_MR_CHMODE_LOOP (2U << 14) +#define USART_MR_CHMODE_REMLOOP (3U << 14) +#define USART_MR_MSBF (1U << 16) +#define USART_MR_MODE9 (1U << 17) +#define USART_MR_CKLO_SCK (1U << 18) +#define USART_MR_OVER16 0 +#define USART_MR_OVER8 (1U << 19) +#define USART_MR_INACK (1U << 20) /* Inhibit NACK generation */ +#define USART_MR_DSNACK (1U << 21) /* Disable Successive NACK */ +#define USART_MR_MAXITERATION(x) ((x) << 24) +#define USART_MR_FILTER (1U << 28) /* Filters for Ir lines */ -// USART registers -#define UART_ATMEL_CR 0x0000 -#define UART_ATMEL_MR 0x0004 -#define UART_ATMEL_IER 0x0008 -#define UART_ATMEL_IDR 0x000C -#define UART_ATMEL_IMR 0x0010 -#define UART_ATMEL_CSR 0x0014 -#define UART_ATMEL_RHR 0x0018 -#define UART_ATMEL_THR 0x001C -#define UART_ATMEL_BRGR 0x0020 -#define UART_ATMEL_RTOR 0x0024 -#define UART_ATMEL_TTGR 0x0028 -#define UART_ATMEL_FIDI 0x0040 -#define UART_ATMEL_NER 0x0044 -#define UART_ATMEL_IF 0x0048 -#define UART_ATMEL_MAN 0x0050 -#define UART_ATMEL_US_VERSION 0x00FC +#define USART_IER 0x08 /* Interrupt enable register */ +#define USART_IDR 0x0c /* Interrupt disable register */ +#define USART_IMR 0x10 /* Interrupt mask register */ +#define USART_CSR 0x14 /* Channel status register */ -// USART Control register -#define UART_ATMEL_CR_RTDIS 19 -#define UART_ATMEL_CR_RTDIS_SIZE 1 -#define UART_ATMEL_CR_RTSEN 18 -#define UART_ATMEL_CR_RTSEN_SIZE 1 -#define UART_ATMEL_CR_RETTO 15 -#define UART_ATMEL_CR_RETTO_SIZE 1 -#define UART_ATMEL_CR_RSTNACK 14 -#define UART_ATMEL_CR_RSTNACK_SIZE 1 -#define UART_ATMEL_CR_RSTIT 13 -#define UART_ATMEL_CR_RSTIT_SIZE 1 -#define UART_ATMEL_CR_SENDA 12 -#define UART_ATMEL_CR_SENDA_SIZE 1 -#define UART_ATMEL_CR_STTTO 11 -#define UART_ATMEL_CR_STTTO_SIZE 1 -#define UART_ATMEL_CR_STPBRK 10 -#define UART_ATMEL_CR_STPBRK_SIZE 1 -#define UART_ATMEL_CR_STTBRK 9 -#define UART_ATMEL_CR_STTBRK_SIZE 1 -#define UART_ATMEL_CR_RSTSTA 8 -#define UART_ATMEL_CR_RSTSTA_SIZE 1 -#define UART_ATMEL_CR_TXDIS 7 -#define UART_ATMEL_CR_TXDIS_SIZE 1 -#define UART_ATMEL_CR_TXEN 6 -#define UART_ATMEL_CR_TXEN_SIZE 1 -#define UART_ATMEL_CR_RXDIS 5 -#define UART_ATMEL_CR_RXDIS_SIZE 1 -#define UART_ATMEL_CR_RXEN 4 -#define UART_ATMEL_CR_RXEN_SIZE 1 -#define UART_ATMEL_CR_RSTTX 3 -#define UART_ATMEL_CR_RSTTX_SIZE 1 -#define UART_ATMEL_CR_RSTRX 2 -#define UART_ATMEL_CR_RSTRX_SIZE 1 +#define USART_CSR_RXRDY (1UL << 0) /* Receiver ready */ +#define USART_CSR_TXRDY (1UL << 1) /* Transmitter ready */ +#define USART_CSR_RXBRK (1UL << 2) /* Break received */ +#define USART_CSR_ENDRX (1UL << 3) /* End of Transfer RX from PDC */ +#define USART_CSR_ENDTX (1UL << 4) /* End of Transfer TX from PDC */ +#define USART_CSR_OVRE (1UL << 5) /* Overrun error */ +#define USART_CSR_FRAME (1UL << 6) /* Framing error */ +#define USART_CSR_PARE (1UL << 7) /* Parity Error */ +#define USART_CSR_TIMEOUT (1UL << 8) /* Timeout since start-timeout */ +#define USART_CSR_TXEMPTY (1UL << 9) /* Transmitter empty */ +#define USART_CSR_ITERATION (1UL << 10) /* max repetitions since RSIT */ +#define USART_CSR_TXBUFE (1UL << 11) /* Buffer empty from PDC */ +#define USART_CSR_RXBUFF (1UL << 12) /* Buffer full from PDC */ +#define USART_CSR_NACK (1UL << 13) /* NACK since last RSTNACK */ +#define USART_CSR_RIIC (1UL << 16) /* RI delta since last csr read */ +#define USART_CSR_DSRIC (1UL << 17) /* DSR delta */ +#define USART_CSR_DCDIC (1UL << 18) /* DCD delta */ +#define USART_CSR_CTSIC (1UL << 19) /* CTS delta */ +#define USART_CSR_RI (1UL << 20) /* RI status */ +#define USART_CSR_DSR (1UL << 21) /* DSR status */ +#define USART_CSR_DCD (1UL << 22) /* DCD status */ +#define USART_CSR_CTS (1UL << 23) /* CTS status */ -// USART Mode register -#define UART_ATMEL_MR_ONEBIT 31 -#define UART_ATMEL_MR_ONEBIT_SIZE 1 -#define UART_ATMEL_MR_MODSYNC 30 -#define UART_ATMEL_MR_MODSYNC_SIZE 1 -#define UART_ATMEL_MR_MAN 29 -#define UART_ATMEL_MR_MAN_SIZE 1 -#define UART_ATMEL_MR_FILTER 28 -#define UART_ATMEL_MR_FILTER_SIZE 1 -#define UART_ATMEL_MR_MAX_ITERATION 26 -#define UART_ATMEL_MR_MAX_ITERATION_SIZ 3 -#define UART_ATMEL_MR_VAR_SYNC 22 -#define UART_ATMEL_MR_VAR_SYNC_SIZE 1 -#define UART_ATMEL_MR_DSNACK 21 -#define UART_ATMEL_MR_DSNACK_SIZE 1 -#define UART_ATMEL_MR_INACK 20 -#define UART_ATMEL_MR_INACK_SIZE 1 -#define UART_ATMEL_MR_OVER 19 -#define UART_ATMEL_MR_OVER_SIZE 1 -#define UART_ATMEL_MR_CLKO 18 -#define UART_ATMEL_MR_CLKO_SIZE 1 -#define UART_ATMEL_MR_MODE9 17 -#define UART_ATMEL_MR_MODE9_SIZE 1 -#define UART_ATMEL_MR_MSBF 16 -#define UART_ATMEL_MR_MSBF_SIZE 1 -#define UART_ATMEL_MR_CHMOD 15 -#define UART_ATMEL_MR_CHMOD_SIZE 2 -#define UART_ATMEL_MR_NBSTOP 13 -#define UART_ATMEL_MR_NBSTOP_SIZE 2 -#define UART_ATMEL_MR_PAR 11 -#define UART_ATMEL_MR_PAR_SIZE 3 -#define UART_ATMEL_MR_SYNC 8 -#define UART_ATMEL_MR_SYN_SIZEC 1 -#define UART_ATMEL_MR_CHRL 7 -#define UART_ATMEL_MR_CHRL_SIZE 2 -#define UART_ATMEL_MR_USCLKS 5 -#define UART_ATMEL_MR_USCLKS_SIZE 2 -#define UART_ATMEL_MR_MODE 3 -#define UART_ATMEL_MR_MODE_SIZE 4 - -// USERT Interrupt Enable Register -#define UART_ATMEL_IER_MANE 20 -#define UART_ATMEL_IER_MANE_SIZE 1 -#define UART_ATMEL_IER_CTSIC 19 -#define UART_ATMEL_IER_CTSIC_SIZE 1 -#define UART_ATMEL_IER_NACK 13 -#define UART_ATMEL_IER_NACK_SIZE 1 -#define UART_ATMEL_IER_RXBUFF 12 -#define UART_ATMEL_IER_RXBUFF_SIZE 1 -#define UART_ATMEL_IER_TXBUFE 11 -#define UART_ATMEL_IER_TXBUFE_SIZE 1 -#define UART_ATMEL_IER_ITERATION 10 -#define UART_ATMEL_IER_ITERATION_SIZE 1 -#define UART_ATMEL_IER_TXEMPTY 9 -#define UART_ATMEL_IER_TXEMPTY_SIZE 1 -#define UART_ATMEL_IER_TIMEOUT 8 -#define UART_ATMEL_IER_TIMEOUT_SIZE 1 -#define UART_ATMEL_IER_PARE 7 -#define UART_ATMEL_IER_PARE_SIZE 1 -#define UART_ATMEL_IER_FRAME 6 -#define UART_ATMEL_IER_FRAME_SIZE 1 -#define UART_ATMEL_IER_OVRE 5 -#define UART_ATMEL_IER_OVRE_SIZE 1 -#define UART_ATMEL_IER_ENDTX 4 -#define UART_ATMEL_IER_ENDTX_SIZE 1 -#define UART_ATMEL_IER_ENDRX 3 -#define UART_ATMEL_IER_ENDRX_SIZE 1 -#define UART_ATMEL_IER_RXBRK 2 -#define UART_ATMEL_IER_RXBRK_SIZE 1 -#define UART_ATMEL_IER_TXRDY 1 -#define UART_ATMEL_IER_TXRDY_SIZE 1 -#define UART_ATMEL_IER_RXRDY 0 -#define UART_ATMEL_IER_RXRDY_SIZE 1 - -// USERT Interrupt Disable Register -#define UART_ATMEL_IDR_MANE 20 -#define UART_ATMEL_IDR_MANE_SIZE 1 -#define UART_ATMEL_IDR_CTSIC 19 -#define UART_ATMEL_IDR_CTSIC_SIZE 1 -#define UART_ATMEL_IDR_NACK 13 -#define UART_ATMEL_IDR_NACK_SIZE 1 -#define UART_ATMEL_IDR_RXBUFF 12 -#define UART_ATMEL_IDR_RXBUFF_SIZE 1 -#define UART_ATMEL_IDR_TXBUFE 11 -#define UART_ATMEL_IDR_TXBUFE_SIZE 1 -#define UART_ATMEL_IDR_ITERATION 10 -#define UART_ATMEL_IDR_ITERATION_SIZE 1 -#define UART_ATMEL_IDR_TXEMPTY 9 -#define UART_ATMEL_IDR_TXEMPTY_SIZE 1 -#define UART_ATMEL_IDR_TIMEOUT 8 -#define UART_ATMEL_IDR_TIMEOUT_SIZE 1 -#define UART_ATMEL_IDR_PARE 7 -#define UART_ATMEL_IDR_PARE_SIZE 1 -#define UART_ATMEL_IDR_FRAME 6 -#define UART_ATMEL_IDR_FRAME_SIZE 1 -#define UART_ATMEL_IDR_OVRE 5 -#define UART_ATMEL_IDR_OVRE_SIZE 1 -#define UART_ATMEL_IDR_ENDTX 4 -#define UART_ATMEL_IDR_ENDTX_SIZE 1 -#define UART_ATMEL_IDR_ENDRX 3 -#define UART_ATMEL_IDR_ENDRX_SIZE 1 -#define UART_ATMEL_IDR_RXBRK 2 -#define UART_ATMEL_IDR_RXBRK_SIZE 1 -#define UART_ATMEL_IDR_TXRDY 1 -#define UART_ATMEL_IDR_TXRDY_SIZE 1 -#define UART_ATMEL_IDR_RXRDY 0 -#define UART_ATMEL_IDR_RXRDY_SIZE 1 - -// USART Interrupt Mask Register -#define UART_ATMEL_IMR_MANE 20 -#define UART_ATMEL_IMR_MANE_SIZE 1 -#define UART_ATMEL_IMR_CTSIC 19 -#define UART_ATMEL_IMR_CTSIC_SIZE 1 -#define UART_ATMEL_IMR_NACK 13 -#define UART_ATMEL_IMR_NACK_SIZE 1 -#define UART_ATMEL_IMR_RXBUFF 12 -#define UART_ATMEL_IMR_RXBUFF_SIZE 1 -#define UART_ATMEL_IMR_TXBUFE 11 -#define UART_ATMEL_IMR_TXBUFE_SIZE 1 -#define UART_ATMEL_IMR_ITERATION 10 -#define UART_ATMEL_IMR_ITERATION_SIZE 1 -#define UART_ATMEL_IMR_TXEMPTY 9 -#define UART_ATMEL_IMR_TXEMPTY_SIZE 1 -#define UART_ATMEL_IMR_TIMEOUT 8 -#define UART_ATMEL_IMR_TIMEOUT_SIZE 1 -#define UART_ATMEL_IMR_PARE 7 -#define UART_ATMEL_IMR_PARE_SIZE 1 -#define UART_ATMEL_IMR_FRAME 6 -#define UART_ATMEL_IMR_FRAME_SIZE 1 -#define UART_ATMEL_IMR_OVRE 5 -#define UART_ATMEL_IMR_OVRE_SIZE 1 -#define UART_ATMEL_IMR_ENDTX 4 -#define UART_ATMEL_IMR_ENDTX_SIZE 1 -#define UART_ATMEL_IMR_ENDRX 3 -#define UART_ATMEL_IMR_ENDRX_SIZE 1 -#define UART_ATMEL_IMR_RXBRK 2 -#define UART_ATMEL_IMR_RXBRK_SIZE 1 -#define UART_ATMEL_IMR_TXRDY 1 -#define UART_ATMEL_IMR_TXRDY_SIZE 1 -#define UART_ATMEL_IMR_RXRDY 0 -#define UART_ATMEL_IMR_RXRDY_SIZE 1 - -// USART Channel Status Register -#define UART_ATMEL_CSR_MANERR 24 -#define UART_ATMEL_CSR_MANERR_SIZE 1 -#define UART_ATMEL_CSR_CTS 23 -#define UART_ATMEL_CSR_CTS_SIZE 1 -#define UART_ATMEL_CSR_CTSIC 19 -#define UART_ATMEL_CSR_CTSIC_SIZE 1 -#define UART_ATMEL_CSR_NACK 13 -#define UART_ATMEL_CSR_NACK_SIZE 1 -#define UART_ATMEL_CSR_RXBUFF 12 -#define UART_ATMEL_CSR_RXBUFF_SIZE 1 -#define UART_ATMEL_CSR_TXBUFE 11 -#define UART_ATMEL_CSR_TXBUFE_SIZE 1 -#define UART_ATMEL_CSR_ITERATION 10 -#define UART_ATMEL_CSR_ITERATION_SIZE 1 -#define UART_ATMEL_CSR_TXEMPTY 9 -#define UART_ATMEL_CSR_TXEMPTY_SIZE 1 -#define UART_ATMEL_CSR_TIMEOUT 8 -#define UART_ATMEL_CSR_TIMEOUT_SIZE 1 -#define UART_ATMEL_CSR_PARE 7 -#define UART_ATMEL_CSR_PARE_SIZE 1 -#define UART_ATMEL_CSR_FRAME 6 -#define UART_ATMEL_CSR_FRAME_SIZE 1 -#define UART_ATMEL_CSR_OVRE 5 -#define UART_ATMEL_CSR_OVRE_SIZE 1 -#define UART_ATMEL_CSR_ENDTX 4 -#define UART_ATMEL_CSR_ENDTX_SIZE 1 -#define UART_ATMEL_CSR_ENDRX 3 -#define UART_ATMEL_CSR_ENDRX_SIZE 1 -#define UART_ATMEL_CSR_RXBRK 2 -#define UART_ATMEL_CSR_RXBRK_SIZE 1 -#define UART_ATMEL_CSR_TXRDY 1 -#define UART_ATMEL_CSR_TXRDY_SIZE 1 -#define UART_ATMEL_CSR_RXRDY 0 -#define UART_ATMEL_CSR_RXRDY_SIZE 1 - -// USART Receive Holding Register -#define UART_ATMEL_RHR_RXSYNH 15 -#define UART_ATMEL_RHR_RXSYNH_SIZE 1 -#define UART_ATMEL_RHR_RXCHR 8 -#define UART_ATMEL_RHR_RXCHR_SIZE 9 - -// USART Transmit Holding Register -#define UART_ATMEL_THR_TXSYNCH 15 -#define UART_ATMEL_THR_TXSYNH_SIZE 1 -#define UART_ATMEL_THR_TXCHR 8 -#define UART_ATMEL_THR_TXCHR_SIZE 9 - -// USART Baudrate generator register -#define UART_ATMEL_BRGR_FP 18 -#define UART_ATMEL_BRGR_FP_SIZE 3 -#define UART_ATMEL_BRGR_CD 15 -#define UART_ATMEL_BRGR_CD_SIZE 16 - -// USART Reciver Time-out Register -#define UART_ATMEL_RTOR_TO 15 -#define UART_ATMEL_RTOR_TO_SIZE 16 - -// USART Transmitter Timeguard Register -#define UART_ATMEL_TTGR_TG 7 -#define UART_ATMEL_TTGR_TG_SIZE 8 - -// USART Fi DI Ratio Register -#define UART_ATMEL_FIDI_FI_DI_RATIO 10 -#define UART_ATMEL_FIDI_FI_DI_RATIO_SIZE 11 +#define USART_RHR 0x18 /* Receiver holding register */ +#define USART_THR 0x1c /* Transmitter holding register */ +#define USART_BRGR 0x20 /* Baud rate generator register */ +#define USART_RTOR 0x24 /* Receiver time-out register */ +#define USART_TTR 0x28 /* Transmitter timeguard register */ +/* 0x2c to 0x3c reserved */ +#define USART_FDRR 0x40 /* FI DI ratio register */ +#define USART_NER 0x44 /* Number of errors register */ +/* 0x48 reserved */ +#define USART_IFR 0x48 /* IrDA filter register */ -// USART Number of Errors Register -#define UART_ATMEL_NB_ERRORS 7 -#define UART_ATMEL_NB_ERRORS_SIZE 8 - -// USART Manchester Configuration Register -#define UART_ATMEL_MAN_DRIFT 30 -#define UART_ATMEL_MAN_DRIFT_SIZE 1 -#define UART_ATMEL_MAN_RX_MPOL 28 -#define UART_ATMEL_MAN_RX_MPOL_SIZE 1 -#define UART_ATMEL_MAN_RX_PP 25 -#define UART_ATMEL_MAN_RX_PP_SIZE 2 -#define UART_ATMEL_MAN_RX_PL 19 -#define UART_ATMEL_MAN_RX_PL_SIZE 4 -#define UART_ATMEL_MAN_TX_MPOL 12 -#define UART_ATMEL_MAN_TX_MPOL_SIZE 1 -#define UART_ATMEL_MAN_TX_PP 9 -#define UART_ATMEL_MAN_TX_PP_SIZE 2 -#define UART_ATMEL_MAN_TX_PL 3 -#define UART_ATMEL_MAN_TX_PL_SIZE 4 - -// USART IrDA Filter Register -#define UART_ATMEL_IF_IRDA_FILTER 7 -#define UART_ATMEL_IF_IRDA_FILTER_SIZE 8 - -// USART Version Register -#define UART_ATMEL_US_VERSION_MFN 18 -#define UART_ATMEL_US_VERSION_MFN_SIZE 3 -#define UART_ATMEL_US_VERSION_VERSION 11 -#define UART_ATMEL_US_VERSION_VERSION_SIZE 12 - #endif /* !_DEV_UART_ATMEL_H_ */ - ==== //depot/projects/avr32/src/sys/dev/uart/uart_bus_atmel.c#4 (text+ko) ==== @@ -74,10 +74,13 @@ switch (device_get_unit(dev)) { case 0: device_set_desc(dev, "USART0"); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); break; case 1: device_set_desc(dev, "USART1"); + /* + * XXX hardwired for ngw100, later do this from hints + */ + sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); break; case 2: device_set_desc(dev, "USART2"); ==== //depot/projects/avr32/src/sys/dev/uart/uart_dev_atmel.c#6 (text+ko) ==== @@ -24,8 +24,6 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * from: src/sys/arm/at91/uart_dev_at91UART_ATMEL.c,v 1.14 2008/05/04 23:29:37 peter - * copyed and stripped out alot of stuff to simplify until i have things booting and then - * places it with a full cross platform usart code for at32 and at91 */ #include <sys/cdefs.h> @@ -51,11 +49,44 @@ #include <machine/bus.h> #include <machine/resource.h> #include <machine/reg.h> -#include <machine/reg_usart.h> -#include <machine/debug.h> +#include <machine/reg_pdc.h> #include "uart_if.h" +#define USART_BUFFER_SIZE 128 + +struct uart_atmel_rx { + bus_addr_t pa; + uint8_t buffer[USART_BUFFER_SIZE]; + bus_dmamap_t map; +}; + +struct uart_atmel_softc { + struct uart_softc base; + bus_dma_tag_t dmatag; /* bus dma tag for mbufs */ + bus_dmamap_t tx_map; + uint32_t flags; +#define HAS_TIMEOUT 1 + struct uart_atmel_rx ping_pong[2]; + struct uart_atmel_rx *ping; + struct uart_atmel_rx *pong; +}; + +#define RD4(bas, reg) \ + bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) +#define WR4(bas, reg, value) \ + bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) + + +#define SIGCHG(c, i, s, d) \ + do { \ + if (c) { \ + i |= (i & s) ? s : s | d; \ + } else { \ + i = (i & s) ? (i & ~s) | d : i; \ + } \ + } while (0); + /* Prototypes */ static int uart_atmel_probe(struct uart_bas *); static void uart_atmel_init(struct uart_bas *, int, int, int, int); @@ -63,6 +94,7 @@ static void uart_atmel_putc(struct uart_bas *, int); static int uart_atmel_rxready(struct uart_bas *); static int uart_atmel_getc(struct uart_bas *bas, struct mtx *mtx); +static __inline void uart_atmel_rx_put(struct uart_softc *sc, int key); static int atmel_usart_bus_probe(struct uart_softc *); static int atmel_usart_bus_attach(struct uart_softc *); static int atmel_usart_bus_detach(struct uart_softc *); @@ -108,6 +140,105 @@ }; +static int +uart_atmel_param(struct uart_bas *bas, int baudrate, int databits, + int stopbits, int parity) +{ + uint32_t mr; + + /* + * Assume 3-write RS-232 configuration. + * XXX Not sure how uart will present the other modes to us, so + * XXX they are unimplemented. maybe ioctl? + */ + mr = USART_MR_MODE_NORMAL; + mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ + + /* + * Or in the databits requested + */ + if (databits < 9) + mr &= ~USART_MR_MODE9; + switch (databits) { + case 5: + mr |= USART_MR_CHRL_5BITS; + break; + case 6: + mr |= USART_MR_CHRL_6BITS; + break; + case 7: + mr |= USART_MR_CHRL_7BITS; + break; + case 8: + mr |= USART_MR_CHRL_8BITS; + break; + case 9: + mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; + break; + default: + return (EINVAL); + } + + /* + * Or in the parity + */ + switch (parity) { + case UART_PARITY_NONE: + mr |= USART_MR_PAR_NONE; + break; + case UART_PARITY_ODD: + mr |= USART_MR_PAR_ODD; + break; + case UART_PARITY_EVEN: + mr |= USART_MR_PAR_EVEN; + break; + case UART_PARITY_MARK: + mr |= USART_MR_PAR_MARK; + break; + case UART_PARITY_SPACE: + mr |= USART_MR_PAR_SPACE; + break; + default: + return (EINVAL); + } + + /* + * Or in the stop bits. Note: The hardware supports 1.5 stop + * bits in async mode, but there's no way to specify that + * AFAICT. Instead, rely on the convention documented at + * http://www.lammertbies.nl/comm/info/RS-232_specs.html which + * states that 1.5 stop bits are used for 5 bit bytes and + * 2 stop bits only for longer bytes. + */ + if (stopbits == 1) + mr |= USART_MR_NBSTOP_1; + else if (databits > 5) + mr |= USART_MR_NBSTOP_2; + else + mr |= USART_MR_NBSTOP_1_5; + + /* + * We want normal plumbing mode too, none of this fancy + * loopback or echo mode. + */ + mr |= USART_MR_CHMODE_NORMAL; + + mr &= ~USART_MR_MSBF; /* lsb first */ + mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ + + WR4(bas, USART_MR, mr); + + /* + * Set the baud rate + * XXX: Skip this for now, clock framework is needed and its alredy set + * by uboot for ngw100. + */ + //WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); + + /* XXX Need to take possible synchronous mode into account */ + return (0); +} + /* * Probe for uart */ @@ -121,21 +252,15 @@ * Init uart for use as console */ static void -uart_atmel_init(struct uart_bas *bas, int baudrate, int databit, int stopbit, +uart_atmel_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { - // todo: Need to fix this - //uart_atmel_param(bas, baudrate, databits, stopbits, parity); + uart_atmel_param(bas, baudrate, databits, stopbits, parity); /* Reset the rx and tx buffers and turn on rx and tx */ - uart_setreg_4(bas, UART_ATMEL_CR, - (1 << UART_ATMEL_CR_RSTSTA) | - (1 << UART_ATMEL_CR_RSTRX) | - (1 << UART_ATMEL_CR_RSTTX)); - uart_setreg_4(bas, UART_ATMEL_CR, - (1 << UART_ATMEL_CR_RXEN) | - (1 << UART_ATMEL_CR_TXEN)); - uart_setreg_4(bas, UART_ATMEL_IDR, 0xffffffff); + WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); + WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); + WR4(bas, USART_IDR, 0xffffffff); } /* @@ -154,10 +279,9 @@ static void uart_atmel_putc(struct uart_bas *bas, int c) { - while (!(uart_getreg_4(bas, UART_ATMEL_CSR) & (1 << UART_ATMEL_CSR_TXRDY))) + while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) continue; - - uart_setreg_4(bas, UART_ATMEL_THR, c); + WR4(bas, USART_THR, c); } /* @@ -166,7 +290,7 @@ static int uart_atmel_rxready(struct uart_bas *bas) { - return ((uart_getreg_4(bas, UART_ATMEL_CSR) & (1 << UART_ATMEL_CSR_RXRDY)) != 0 ? 1 : 0); + return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); } /* @@ -176,11 +300,9 @@ uart_atmel_getc(struct uart_bas *bas, struct mtx *mtx) { int c; - - while (!(uart_getreg_4(bas, UART_ATMEL_CSR) & (1 << UART_ATMEL_CSR_RXRDY))) + while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) continue; - - c = uart_getreg_4(bas, UART_ATMEL_RHR); + c = RD4(bas, USART_RHR); c &= 0xff; return (c); } @@ -191,12 +313,131 @@ return (0); } +#ifndef SKYEYE_WORKAROUNDS +static void +uart_atmel_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + if (error != 0) + return; + *(bus_addr_t *)arg = segs[0].ds_addr; +} +#endif + static int atmel_usart_bus_attach(struct uart_softc *sc) { +#ifndef SKYEYE_WORKAROUNDS + int err; + int i; +#endif + uint32_t cr; + struct uart_atmel_softc *atsc; + struct uart_devinfo *di; + + atsc = (struct uart_atmel_softc *)sc; + /* Enable device clock */ devclk_enable(sc->sc_dev); + + sc->sc_txfifosz = USART_BUFFER_SIZE; + sc->sc_rxfifosz = USART_BUFFER_SIZE; + sc->sc_hwiflow = 0; + + /* + * XXX: Enableing interrupts and PDC creates races between sysdev pools + * and the dma + */ + if (sc->sc_sysdev != NULL) { + di = sc->sc_sysdev; + uart_atmel_init(&sc->sc_bas, di->baudrate, di->databits, di->stopbits, + di->parity); + return(0); + } + + /* + * See if we have a TIMEOUT bit. We disable all interrupts as + * a side effect. Boot loaders may have enabled them. Since + * a TIMEOUT interrupt can't happen without other setup, the + * apparent race here can't actually happen. + */ + WR4(&sc->sc_bas, USART_IDR, 0xffffffff); + WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); + if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) + atsc->flags |= HAS_TIMEOUT; + WR4(&sc->sc_bas, USART_IDR, 0xffffffff); + +#ifndef SKYEYE_WORKAROUNDS + /* + * Allocate DMA tags and maps + */ + err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, + NULL, &atsc->dmatag); + if (err != 0) + goto errout; + err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map); + if (err != 0) + goto errout; + if (atsc->flags & HAS_TIMEOUT) { + for (i = 0; i < 2; i++) { + err = bus_dmamap_create(atsc->dmatag, 0, + &atsc->ping_pong[i].map); + if (err != 0) + goto errout; + err = bus_dmamap_load(atsc->dmatag, + atsc->ping_pong[i].map, + atsc->ping_pong[i].buffer, sc->sc_rxfifosz, + uart_atmel_getaddr, &atsc->ping_pong[i].pa, 0); + if (err != 0) + goto errout; + bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map, + BUS_DMASYNC_PREREAD); + } + atsc->ping = &atsc->ping_pong[0]; + atsc->pong = &atsc->ping_pong[1]; + } +#endif + + /* + * Prime the pump with the RX buffer. We use two 64 byte bounce + * buffers here to avoid data overflow. + */ + + /* Turn on rx and tx */ + cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; + WR4(&sc->sc_bas, USART_CR, cr); + WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); + + /* + * Setup the PDC to receive data. We use the ping-pong buffers + * so that we can more easily bounce between the two and so that + * we get an interrupt 1/2 way through the software 'fifo' we have + * to avoid overruns. + */ + if (atsc->flags & HAS_TIMEOUT) { + WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); + WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); + WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); + WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); + WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); + + /* Set the receive timeout to be 1.5 character times. */ + WR4(&sc->sc_bas, USART_RTOR, 12); + WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); + WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | + USART_CSR_RXBUFF | USART_CSR_ENDRX); + } else { + WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); + } + WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK); +#ifndef SKYEYE_WORKAROUNDS +errout:; + // XXX bad + return (err); +#else return (0); +#endif } static int @@ -216,48 +457,269 @@ static int atmel_usart_bus_getsig(struct uart_softc *sc) { - return (0); avr32_impl(); + uint32_t new, sig; + uint8_t csr; + + uart_lock(sc->sc_hwmtx); + csr = RD4(&sc->sc_bas, USART_CSR); + sig = 0; + if (csr & USART_CSR_CTS) + sig |= SER_CTS; + if (csr & USART_CSR_DCD) + sig |= SER_DCD; + if (csr & USART_CSR_DSR) + sig |= SER_DSR; + if (csr & USART_CSR_RI) + sig |= SER_RI; + new = sig & ~SER_MASK_DELTA; + sc->sc_hwsig = new; + uart_unlock(sc->sc_hwmtx); + return (sig); } static int atmel_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) { - return (0); avr32_impl(); + switch (request) { + case UART_IOCTL_BREAK: + case UART_IOCTL_IFLOW: + case UART_IOCTL_OFLOW: + break; + case UART_IOCTL_BAUD: + panic("Need to fix clock stuff jarr"); + //WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data)); + return (0); + } + return (EINVAL); } +static __inline void +uart_atmel_rx_put(struct uart_softc *sc, int key) +{ +#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER) + int kdb_brk; + + if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { + if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) { + switch (kdb_brk) { + case KDB_REQ_DEBUGGER: + kdb_enter(KDB_WHY_BREAK, + "Break sequence on console"); + break; + case KDB_REQ_PANIC: + kdb_panic("Panic sequence on console"); + break; + case KDB_REQ_REBOOT: + kdb_reboot(); + break; + } + } + } +#endif + uart_rx_put(sc, key); +} + static int atmel_usart_bus_ipend(struct uart_softc *sc) { - return (0); + int csr = RD4(&sc->sc_bas, USART_CSR); + int ipend = 0, i, len; + struct uart_atmel_softc *atsc; + struct uart_atmel_rx *p; + + atsc = (struct uart_atmel_softc *)sc; + if (csr & USART_CSR_ENDTX) { + bus_dmamap_sync(atsc->dmatag, atsc->tx_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(atsc->dmatag, atsc->tx_map); + } + uart_lock(sc->sc_hwmtx); + if (csr & USART_CSR_TXRDY) { + if (sc->sc_txbusy) + ipend |= SER_INT_TXIDLE; + WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY); + } + if (csr & USART_CSR_ENDTX) { + if (sc->sc_txbusy) + ipend |= SER_INT_TXIDLE; + WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX); + } + + /* + * Due to the contraints of the DMA engine present in the + * atmel chip, I can't just say I have a rx interrupt pending + * and do all the work elsewhere. I need to look at the CSR + * bits right now and do things based on them to avoid races. + */ + if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) { + // Have a buffer overflow. Copy all data from both + // ping and pong. Insert overflow character. Reset + // ping and pong and re-enable the PDC to receive + // characters again. + bus_dmamap_sync(atsc->dmatag, atsc->ping->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(atsc->dmatag, atsc->pong->map, + BUS_DMASYNC_POSTREAD); + for (i = 0; i < sc->sc_rxfifosz; i++) + uart_atmel_rx_put(sc, atsc->ping->buffer[i]); + for (i = 0; i < sc->sc_rxfifosz; i++) + uart_atmel_rx_put(sc, atsc->pong->buffer[i]); + uart_rx_put(sc, UART_STAT_OVERRUN); + csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT); + WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); + WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); + WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); + WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); + WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); + ipend |= SER_INT_RXREADY; + } + if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) { + // Shuffle data from 'ping' of ping pong buffer, but + // leave current 'pong' in place, as it has become the + // new 'ping'. We need to copy data and setup the old + // 'ping' as the new 'pong' when we're done. + bus_dmamap_sync(atsc->dmatag, atsc->ping->map, + BUS_DMASYNC_POSTREAD); + for (i = 0; i < sc->sc_rxfifosz; i++) + uart_atmel_rx_put(sc, atsc->ping->buffer[i]); + p = atsc->ping; + atsc->ping = atsc->pong; + atsc->pong = p; + WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); + WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); + ipend |= SER_INT_RXREADY; + } + if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) { + // We have one partial buffer. We need to stop the + // PDC, get the number of characters left and from + // that compute number of valid characters. We then + // need to reset ping and pong and reenable the PDC. + // Not sure if there's a race here at fast baud rates + // we need to worry about. + WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); + bus_dmamap_sync(atsc->dmatag, atsc->ping->map, + BUS_DMASYNC_POSTREAD); + len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); + for (i = 0; i < len; i++) + uart_atmel_rx_put(sc, atsc->ping->buffer[i]); + WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); + WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); + WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); + WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); + ipend |= SER_INT_RXREADY; + } + if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) { + // We have another charater in a device that doesn't support + // timeouts, so we do it one character at a time. + uart_atmel_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); + ipend |= SER_INT_RXREADY; + } + + if (csr & USART_CSR_RXBRK) { >>> TRUNCATED FOR MAIL (1000 lines) <<<
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