From owner-svn-src-head@freebsd.org Mon May 23 20:07:19 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 860E3B4692D; Mon, 23 May 2016 20:07:19 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5CDC31D7A; Mon, 23 May 2016 20:07:19 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u4NK7IQS066431; Mon, 23 May 2016 20:07:18 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u4NK7HO7066421; Mon, 23 May 2016 20:07:17 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201605232007.u4NK7HO7066421@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Mon, 23 May 2016 20:07:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r300533 - in head/sys/arm: arm at91 cavium/cns11xx include mv X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 May 2016 20:07:19 -0000 Author: ian Date: Mon May 23 20:07:17 2016 New Revision: 300533 URL: https://svnweb.freebsd.org/changeset/base/300533 Log: Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses where possible. In the places that doesn't work (multi-line inline asm, and places where the old armv4 cpufuncs mechanism is used), annotate the accesses with a comment that includes SCTLR. Now a grep -i sctlr can find all the system control register manipulations. No functional changes. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/cpufunc_asm.S head/sys/arm/arm/cpufunc_asm_xscale.S head/sys/arm/arm/elf_trampoline.c head/sys/arm/arm/locore-v4.S head/sys/arm/arm/machdep.c head/sys/arm/at91/at91_machdep.c head/sys/arm/cavium/cns11xx/econa_machdep.c head/sys/arm/include/cpu-v4.h head/sys/arm/mv/mv_machdep.c Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/cpufunc.c Mon May 23 20:07:17 2016 (r300533) @@ -886,7 +886,7 @@ arm9_setup(void) /* Clear out the cache */ cpu_idcache_wbinv_all(); - /* Set the control register */ + /* Set the control register (SCTLR) */ cpu_control(cpuctrlmask, cpuctrl); } Modified: head/sys/arm/arm/cpufunc_asm.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm.S Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/cpufunc_asm.S Mon May 23 20:07:17 2016 (r300533) @@ -68,7 +68,7 @@ ENTRY(cpu_ident) END(cpu_ident) ENTRY(cpu_get_control) - mrc p15, 0, r0, c1, c0, 0 + mrc CP15_SCTLR(r0) RET END(cpu_get_control) @@ -98,13 +98,6 @@ END(cpu_faultaddress) * All other registers are CPU architecture specific */ -#if 0 /* See below. */ -ENTRY(cpufunc_control) - mcr p15, 0, r0, c1, c0, 0 - RET -END(cpufunc_control) -#endif - ENTRY(cpu_domains) mcr p15, 0, r0, c3, c0, 0 RET @@ -121,13 +114,13 @@ END(cpu_domains) */ ENTRY(cpufunc_control) - mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ + mrc CP15_SCTLR(r3) /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there is a change */ - mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ + mcrne CP15_SCTLR(r2) /* Write new control register */ mov r0, r3 /* Return old value */ RET Modified: head/sys/arm/arm/cpufunc_asm_xscale.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_xscale.S Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/cpufunc_asm_xscale.S Mon May 23 20:07:17 2016 (r300533) @@ -111,13 +111,13 @@ END(xscale_cpwait) * changes in the control register. */ ENTRY(xscale_control) - mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ + mrc CP15_SCTLR(r3) /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there was a change */ mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */ - mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ + mcrne CP15_SCTLR(r3) /* Write new control register */ mov r0, r3 /* Return old value */ CPWAIT_AND_RETURN(r1) Modified: head/sys/arm/arm/elf_trampoline.c ============================================================================== --- head/sys/arm/arm/elf_trampoline.c Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/elf_trampoline.c Mon May 23 20:07:17 2016 (r300533) @@ -227,14 +227,14 @@ _startC(void) "bic %0, %0, #0xff000000\n" "and %1, %1, #0xff000000\n" "orr %0, %0, %1\n" - "mrc p15, 0, %1, c1, c0, 0\n" + "mrc p15, 0, %1, c1, c0, 0\n" /* CP15_SCTLR(%1)*/ "bic %1, %1, #1\n" /* Disable MMU */ "orr %1, %1, #(4 | 8)\n" /* Add DC enable, WBUF enable */ "orr %1, %1, #0x1000\n" /* Add IC enable */ "orr %1, %1, #(0x800)\n" /* BPRD enable */ - "mcr p15, 0, %1, c1, c0, 0\n" + "mcr p15, 0, %1, c1, c0, 0\n" /* CP15_SCTLR(%1)*/ "nop\n" "nop\n" "nop\n" @@ -599,9 +599,9 @@ load_kernel(unsigned int kstart, unsigne __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n" "mcr p15, 0, %0, c7, c10, 4\n" : : "r" (curaddr)); - __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" + __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ "bic %0, %0, #1\n" /* MMU_ENABLE */ - "mcr p15, 0, %0, c1, c0, 0\n" + "mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ : "=r" (ssym)); /* Jump to the entry point. */ ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))(); @@ -643,9 +643,9 @@ setup_pagetables(unsigned int pt_addr, v __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */ "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */ "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */ - "mrc p15, 0, %0, c1, c0, 0\n" + "mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ "orr %0, %0, #1\n" /* MMU_ENABLE */ - "mcr p15, 0, %0, c1, c0, 0\n" + "mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */ "mov r0, r0\n" "sub pc, pc, #4\n" : @@ -700,9 +700,9 @@ __start(void) */ cpu_idcache_wbinv_all(); cpu_l2cache_wbinv_all(); - __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" + __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ "bic %0, %0, #1\n" /* MMU_DISABLE */ - "mcr p15, 0, %0, c1, c0, 0\n" + "mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/ :"=r" (pt_addr)); } else #endif Modified: head/sys/arm/arm/locore-v4.S ============================================================================== --- head/sys/arm/arm/locore-v4.S Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/locore-v4.S Mon May 23 20:07:17 2016 (r300533) @@ -114,7 +114,7 @@ ASENTRY_NP(_start) * If we're running with MMU disabled, test against the * physical address instead. */ - mrc p15, 0, r2, c1, c0, 0 + mrc CP15_SCTLR(r2) ands r2, r2, #CPU_CONTROL_MMU_ENABLE ldreq r6, =PHYSADDR ldrne r6, =LOADERRAMADDR @@ -146,12 +146,12 @@ from_ram: disable_mmu: /* Disable MMU for a while */ - mrc p15, 0, r2, c1, c0, 0 + mrc CP15_SCTLR(r2) bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ CPU_CONTROL_WBUF_ENABLE) bic r2, r2, #(CPU_CONTROL_IC_ENABLE) bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE) - mcr p15, 0, r2, c1, c0, 0 + mcr CP15_SCTLR(r2) nop nop @@ -213,9 +213,9 @@ Lunmapped: /* * Enable MMU. */ - mrc p15, 0, r0, c1, c0, 0 + mrc CP15_SCTLR(r0) orr r0, r0, #(CPU_CONTROL_MMU_ENABLE) - mcr p15, 0, r0, c1, c0, 0 + mcr CP15_SCTLR(r0) nop nop nop @@ -398,7 +398,7 @@ ENTRY_NP(cpu_halt) * Hurl ourselves into the ROM */ mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) - mcr p15, 0, r0, c1, c0, 0 + mcr CP15_SCTLR(r0) mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ mov pc, r4 Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/arm/machdep.c Mon May 23 20:07:17 2016 (r300533) @@ -416,20 +416,15 @@ arm_vector_init(vm_offset_t va, int whic if (va == ARM_VECTORS_HIGH) { /* - * Assume the MD caller knows what it's doing here, and - * really does want the vector page relocated. + * Enable high vectors in the system control reg (SCTLR). + * + * Assume the MD caller knows what it's doing here, and really + * does want the vector page relocated. * * Note: This has to be done here (and not just in * cpu_setup()) because the vector page needs to be * accessible *before* cpu_startup() is called. * Think ddb(9) ... - * - * NOTE: If the CPU control register is not readable, - * this will totally fail! We'll just assume that - * any system that has high vector support has a - * readable CPU control register, for now. If we - * ever encounter one that does not, we'll have to - * rethink this. */ cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); } Modified: head/sys/arm/at91/at91_machdep.c ============================================================================== --- head/sys/arm/at91/at91_machdep.c Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/at91/at91_machdep.c Mon May 23 20:07:17 2016 (r300533) @@ -584,6 +584,10 @@ initarm(struct arm_boot_params *abp) memsize = 16 * 1024 * 1024; } + /* Enable MMU (set SCTLR), and do other cpu-specific setup. */ + cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); + cpu_setup(); + /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. @@ -592,9 +596,6 @@ initarm(struct arm_boot_params *abp) * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ - cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); - cpu_setup(); - set_stackptrs(0); /* Modified: head/sys/arm/cavium/cns11xx/econa_machdep.c ============================================================================== --- head/sys/arm/cavium/cns11xx/econa_machdep.c Mon May 23 19:52:08 2016 (r300532) +++ head/sys/arm/cavium/cns11xx/econa_machdep.c Mon May 23 20:07:17 2016 (r300533) @@ -272,6 +272,9 @@ initarm(struct arm_boot_params *abp) mem_info = ((*ddr) >> 4) & 0x3; memsize = (8< #include +#include #include #include #include #include +#if __ARM_ARCH < 6 +#include +#else +#include +#endif + #include /* XXX */ #include /* XXX eventually this should be eliminated */ #include @@ -453,9 +460,9 @@ DB_SHOW_COMMAND(cp15, db_show_cp15) __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); db_printf("Current Cache Lvl ID: 0x%08x\n",reg); - __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); + reg = cp15_sctlr_get(); db_printf("Ctrl: 0x%08x\n",reg); - __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); + reg = cp15_actlr_get(); db_printf("Aux Ctrl: 0x%08x\n",reg); __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));