From owner-cvs-all@FreeBSD.ORG Mon Jun 7 23:01:10 2004 Return-Path: Delivered-To: cvs-all@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id DC3E316A4CE; Mon, 7 Jun 2004 23:01:10 +0000 (GMT) Received: from VARK.homeunix.com (ar59.lsanca2-4.27.98.47.lsanca2.dsl-verizon.net [4.27.98.47]) by mx1.FreeBSD.org (Postfix) with ESMTP id 9B0FA43D54; Mon, 7 Jun 2004 23:01:10 +0000 (GMT) (envelope-from das@FreeBSD.ORG) Received: from VARK.homeunix.com (localhost [127.0.0.1]) by VARK.homeunix.com (8.12.11/8.12.10) with ESMTP id i57N19G4001406; Mon, 7 Jun 2004 16:01:09 -0700 (PDT) (envelope-from das@FreeBSD.ORG) Received: (from das@localhost) by VARK.homeunix.com (8.12.11/8.12.10/Submit) id i57N19Zv001405; Mon, 7 Jun 2004 16:01:09 -0700 (PDT) (envelope-from das@FreeBSD.ORG) Date: Mon, 7 Jun 2004 16:01:09 -0700 From: David Schultz To: David Malone Message-ID: <20040607230109.GA1165@VARK.homeunix.com> Mail-Followup-To: David Malone , src-committers@FreeBSD.ORG, cvs-src@FreeBSD.ORG, cvs-all@FreeBSD.ORG References: <200406060916.i569G2m2097113@repoman.freebsd.org> <20040606091758.GA6354@VARK.homeunix.com> <20040607094321.GA32159@walton.maths.tcd.ie> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20040607094321.GA32159@walton.maths.tcd.ie> cc: cvs-src@FreeBSD.ORG cc: src-committers@FreeBSD.ORG cc: cvs-all@FreeBSD.ORG Subject: Re: cvs commit: src/sys/amd64/amd64 fpu.c X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Jun 2004 23:01:11 -0000 On Mon, Jun 07, 2004, David Malone wrote: > On Sun, Jun 06, 2004 at 02:17:58AM -0700, David Schultz wrote: > > It would be great if someone could pick this up and devise the > > appropriate fix. I want to see this bug fixed, but I don't have the > > hardware to do amd64 kernel hacking. I'm happy to help anyone who is > > interested. > > I think I've figured out the problem. On SMP systems, fpuinit() is > called before enable_sse() for secondary processors. The ldmxcsr > instruction counts as a sse instruction, so you get an illegal > instruction fault. The patch below switches the order of fpuinit() > and enable_sse() and fixes the problem on my system anyway. Nice catch. That would certainly explain the problem, and both of the machines with reported problems (yours and sledge) are SMP. Care to commit this?