Date: Sun, 2 Feb 1997 17:22:34 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: smp@csn.net (Steve Passe) Cc: terry@lambert.org, davem@jenolan.rutgers.edu, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702030022.RAA09838@phaeton.artisoft.com> In-Reply-To: <199702030003.RAA11312@clem.systemsix.com> from "Steve Passe" at Feb 2, 97 05:03:18 pm
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> > What do you have to say about treating the cache line coherency? > > Is it necessary, or is it automatic? > > I don't have a clue. I was under the belief that we have a MESI compliant > board to deal with, but I could easily be wrong about that. You are wrong for the BeBox and the SMP PowerMac PPC603 hardware, which are only MEI (no 'S'). I don't know how Intel-centric you are, but I'd just as soon see an entry under SMP, seperate from the CPU architecture, in the build tree. > Cache flushing: > > The processor can generate special flush and write-back bus cycles > that must be used by external caches in a manner that maintains cache > coherency. The actual responses are implementation-specific and may > vary from design to design. Here's the (possible) stool sample in the flower arrangement... 8-(. If you can attribute his problems to something else, though, I will be very happy. Like I said before, it is more likely that your theory is correct (as you point out, you wrote the APIC_IO code). Regards, Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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