From owner-svn-src-stable@freebsd.org Wed Apr 15 13:59:52 2020 Return-Path: Delivered-To: svn-src-stable@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 86A402B7C2D; Wed, 15 Apr 2020 13:59:52 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 492PB02yzNz3NrR; Wed, 15 Apr 2020 13:59:52 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 612FB1FF7E; Wed, 15 Apr 2020 13:59:52 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 03FDxqR3051857; Wed, 15 Apr 2020 13:59:52 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 03FDxqLc051856; Wed, 15 Apr 2020 13:59:52 GMT (envelope-from mav@FreeBSD.org) Message-Id: <202004151359.03FDxqLc051856@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Wed, 15 Apr 2020 13:59:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r359972 - stable/12/sys/dev/ahci X-SVN-Group: stable-12 X-SVN-Commit-Author: mav X-SVN-Commit-Paths: stable/12/sys/dev/ahci X-SVN-Commit-Revision: 359972 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Apr 2020 13:59:52 -0000 Author: mav Date: Wed Apr 15 13:59:51 2020 New Revision: 359972 URL: https://svnweb.freebsd.org/changeset/base/359972 Log: MFC r359499: Add ID for JMicron JMB582/JMB585 AHCI controller. JMB582 has 2 6Gbps SATA ports and PCIe 3.0 x1. JMB585 has 5 6Gbps SATA ports and PCIe 3.0 x2. Both chips support AHCI v1.31, Port Multiplier with FBS and 8 MSI vectors. Modified: stable/12/sys/dev/ahci/ahci.c stable/12/sys/dev/ahci/ahci.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/ahci/ahci.c ============================================================================== --- stable/12/sys/dev/ahci/ahci.c Wed Apr 15 13:59:09 2020 (r359971) +++ stable/12/sys/dev/ahci/ahci.c Wed Apr 15 13:59:51 2020 (r359972) @@ -141,7 +141,27 @@ int ahci_ctlr_reset(device_t dev) { struct ahci_controller *ctlr = device_get_softc(dev); + uint32_t v; int timeout; + + /* BIOS/OS Handoff */ + if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) && + (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) && + ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) { + + /* Request OS ownership. */ + ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS); + + /* Wait up to 2s for BIOS ownership release. */ + for (timeout = 0; timeout < 80; timeout++) { + DELAY(25000); + v = ATA_INL(ctlr->r_mem, AHCI_BOHC); + if ((v & AHCI_BOHC_BOS) == 0) + break; + if ((v & AHCI_BOHC_BB) == 0) + break; + } + } /* Enable AHCI mode */ ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); Modified: stable/12/sys/dev/ahci/ahci.h ============================================================================== --- stable/12/sys/dev/ahci/ahci.h Wed Apr 15 13:59:09 2020 (r359971) +++ stable/12/sys/dev/ahci/ahci.h Wed Apr 15 13:59:51 2020 (r359972) @@ -214,6 +214,13 @@ #define AHCI_CAP2_SADM 0x00000010 #define AHCI_CAP2_DESO 0x00000020 +#define AHCI_BOHC 0x28 +#define AHCI_BOHC_BOS 0x00000001 +#define AHCI_BOHC_OOS 0x00000002 +#define AHCI_BOHC_SOOE 0x00000004 +#define AHCI_BOHC_OOC 0x00000008 +#define AHCI_BOHC_BB 0x00000010 + #define AHCI_VSCAP 0xa4 #define AHCI_OFFSET 0x100 #define AHCI_STEP 0x80