From owner-svn-src-all@FreeBSD.ORG Tue Mar 15 17:59:31 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 422401065675; Tue, 15 Mar 2011 17:59:31 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 2F2FD8FC0A; Tue, 15 Mar 2011 17:59:31 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id p2FHxVcT053349; Tue, 15 Mar 2011 17:59:31 GMT (envelope-from jkim@svn.freebsd.org) Received: (from jkim@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id p2FHxVNx053347; Tue, 15 Mar 2011 17:59:31 GMT (envelope-from jkim@svn.freebsd.org) Message-Id: <201103151759.p2FHxVNx053347@svn.freebsd.org> From: Jung-uk Kim Date: Tue, 15 Mar 2011 17:59:31 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r219674 - head/share/man/man9 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Mar 2011 17:59:31 -0000 Author: jkim Date: Tue Mar 15 17:59:30 2011 New Revision: 219674 URL: http://svn.freebsd.org/changeset/base/219674 Log: Fix a typo in the previous commit. AMD64 and Intel 64 are two brand names. Modified: head/share/man/man9/get_cyclecount.9 Modified: head/share/man/man9/get_cyclecount.9 ============================================================================== --- head/share/man/man9/get_cyclecount.9 Tue Mar 15 17:19:52 2011 (r219673) +++ head/share/man/man9/get_cyclecount.9 Tue Mar 15 17:59:30 2011 (r219674) @@ -71,7 +71,9 @@ structure returned by .Xr binuptime 9 . .Pp The -.Tn AMD64 and Intel 64 +.Tn AMD64 +and +.Tn Intel 64 processors use the .Li TSC register.