Date: Tue, 24 Oct 2023 04:47:14 GMT From: Zhenlei Huang <zlei@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 95c4e64bf677 - stable/12 - vmx: Prefer consistent naming for loader tunables Message-ID: <202310240447.39O4lEwZ005561@gitrepo.freebsd.org>
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The branch stable/12 has been updated by zlei: URL: https://cgit.FreeBSD.org/src/commit/?id=95c4e64bf677895fde328fcb564224cc2ad2eda1 commit 95c4e64bf677895fde328fcb564224cc2ad2eda1 Author: Zhenlei Huang <zlei@FreeBSD.org> AuthorDate: 2023-10-19 17:18:25 +0000 Commit: Zhenlei Huang <zlei@FreeBSD.org> CommitDate: 2023-10-24 04:46:30 +0000 vmx: Prefer consistent naming for loader tunables The following loader tunables do have corresponding sysctl MIBs but with different names. That may be historical reason. Let's prefer consistent naming for them so that it will be easier to read and maintain. 1. hw.vmm.l1d_flush -> hw.vmm.vmx.l1d_flush 2. hw.vmm.l1d_flush_sw -> hw.vmm.vmx.l1d_flush_sw 3. hw.vmm.vmx.use_apic_pir -> hw.vmm.vmx.cap.posted_interrupts 4. hw.vmm.vmx.use_apic_vid -> hw.vmm.vmx.cap.virtual_interrupt_delivery 5. hw.vmm.vmx.use_tpr_shadowing -> hw.vmm.vmx.cap.tpr_shadowing Old names are kept for compatibility. Meanwhile, add sysctl flag CTLFLAG_TUN to them so that `sysctl -T` will report them correctly. Reviewed by: corvink, jhb, kib, #bhyve MFC after: 5 days Differential Revision: https://reviews.freebsd.org/D42251 (cherry picked from commit f3ff0918ffcdbcb4c39175f3f9be70999edb14e8) (cherry picked from commit 9e48b627aed346bf5e950134a581218d3097eb7c) (cherry picked from commit ba924ff8c46ce44fc9b877cc48bdae3bc966c13a) --- sys/amd64/vmm/intel/vmx.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/sys/amd64/vmm/intel/vmx.c b/sys/amd64/vmm/intel/vmx.c index e800618e9eeb..8ab927af3fc9 100644 --- a/sys/amd64/vmm/intel/vmx.c +++ b/sys/amd64/vmm/intel/vmx.c @@ -181,15 +181,18 @@ SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, invpcid, CTLFLAG_RD, &cap_invpcid, 0, "Guests are allowed to use INVPCID"); static int tpr_shadowing; -SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, tpr_shadowing, CTLFLAG_RD, +SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, tpr_shadowing, + CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &tpr_shadowing, 0, "TPR shadowing support"); static int virtual_interrupt_delivery; -SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, virtual_interrupt_delivery, CTLFLAG_RD, +SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, virtual_interrupt_delivery, + CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &virtual_interrupt_delivery, 0, "APICv virtual interrupt delivery support"); static int posted_interrupts; -SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, posted_interrupts, CTLFLAG_RD, +SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, posted_interrupts, + CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &posted_interrupts, 0, "APICv posted interrupt support"); static int pirvec = -1; @@ -202,10 +205,10 @@ SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD, &vpid_alloc_failed, 0, NULL); int guest_l1d_flush; -SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush, CTLFLAG_RD, +SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &guest_l1d_flush, 0, NULL); int guest_l1d_flush_sw; -SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush_sw, CTLFLAG_RD, +SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush_sw, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &guest_l1d_flush_sw, 0, NULL); static struct msr_entry msr_load_list[1] __aligned(16); @@ -819,8 +822,12 @@ vmx_init(int ipinum) &tmp); if (error == 0) { tpr_shadowing = 1; +#ifndef BURN_BRIDGES TUNABLE_INT_FETCH("hw.vmm.vmx.use_tpr_shadowing", &tpr_shadowing); +#endif + TUNABLE_INT_FETCH("hw.vmm.vmx.cap.tpr_shadowing", + &tpr_shadowing); } if (tpr_shadowing) { @@ -841,8 +848,12 @@ vmx_init(int ipinum) procbased2_vid_bits, 0, &tmp); if (error == 0 && tpr_shadowing) { virtual_interrupt_delivery = 1; +#ifndef BURN_BRIDGES TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_vid", &virtual_interrupt_delivery); +#endif + TUNABLE_INT_FETCH("hw.vmm.vmx.cap.virtual_interrupt_delivery", + &virtual_interrupt_delivery); } if (virtual_interrupt_delivery) { @@ -867,8 +878,12 @@ vmx_init(int ipinum) } } else { posted_interrupts = 1; +#ifndef BURN_BRIDGES TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_pir", &posted_interrupts); +#endif + TUNABLE_INT_FETCH("hw.vmm.vmx.cap.posted_interrupts", + &posted_interrupts); } } } @@ -885,7 +900,10 @@ vmx_init(int ipinum) guest_l1d_flush = (cpu_ia32_arch_caps & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) == 0; +#ifndef BURN_BRIDGES TUNABLE_INT_FETCH("hw.vmm.l1d_flush", &guest_l1d_flush); +#endif + TUNABLE_INT_FETCH("hw.vmm.vmx.l1d_flush", &guest_l1d_flush); /* * L1D cache flush is enabled. Use IA32_FLUSH_CMD MSR when @@ -897,8 +915,12 @@ vmx_init(int ipinum) if (guest_l1d_flush) { if ((cpu_stdext_feature3 & CPUID_STDEXT3_L1D_FLUSH) == 0) { guest_l1d_flush_sw = 1; +#ifndef BURN_BRIDGES TUNABLE_INT_FETCH("hw.vmm.l1d_flush_sw", &guest_l1d_flush_sw); +#endif + TUNABLE_INT_FETCH("hw.vmm.vmx.l1d_flush_sw", + &guest_l1d_flush_sw); } if (guest_l1d_flush_sw) { if (nmi_flush_l1d_sw <= 1)
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