From owner-p4-projects@FreeBSD.ORG Thu Mar 11 19:06:29 2004 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 6B75116A4D0; Thu, 11 Mar 2004 19:06:29 -0800 (PST) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 4627416A4CE for ; Thu, 11 Mar 2004 19:06:29 -0800 (PST) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 40C6143D53 for ; Thu, 11 Mar 2004 19:06:29 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.10/8.12.10) with ESMTP id i2C36TGe019448 for ; Thu, 11 Mar 2004 19:06:29 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.10/8.12.10/Submit) id i2C36Si5019445 for perforce@freebsd.org; Thu, 11 Mar 2004 19:06:28 -0800 (PST) (envelope-from jmallett@freebsd.org) Date: Thu, 11 Mar 2004 19:06:28 -0800 (PST) Message-Id: <200403120306.i2C36Si5019445@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 48750 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Mar 2004 03:06:29 -0000 http://perforce.freebsd.org/chv.cgi?CH=48750 Change 48750 by jmallett@jmallett_oingo on 2004/03/11 19:05:55 Don't do the cute and'ing of bits thing, I don't think I really had a reason. Let alone a good one. Affected files ... .. //depot/projects/mips/sys/mips/mips/locore.S#10 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/locore.S#10 (text+ko) ==== @@ -50,31 +50,23 @@ .set noreorder .text - .globl btext -btext: +GLOBAL(btext) ENTRY(start) /* - * t0: Bits to preserve if set: - * Soft reset - * Boot exception vectors (firmware-provided) - */ - li t0, MIPS_SR_BEV | MIPS_SR_SR - /* - * t1: Bits to set explicitly: + * t0: Bits to set: * Kernel mode is 64-bit * Enable FPU */ - li t1, MIPS_SR_KX | MIPS_SR_COP_1_BIT + li t0, MIPS_SR_KX | MIPS_SR_COP_1_BIT /* * Read coprocessor 0 status register, clear bits not * preserved (namely, clearing interrupt bits), and set * bits we want to explicitly set. */ - mfc0 t2, MIPS_COP_0_STATUS - and t2, t0 - or t2, t1 - mtc0 t2, MIPS_COP_0_STATUS + mfc0 t1, MIPS_COP_0_STATUS + or t1, t0 + mtc0 t1, MIPS_COP_0_STATUS COP0_SYNC /* Extra nops for the FPU to spin up. */