From owner-p4-projects@FreeBSD.ORG Tue Apr 18 19:26:25 2006 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id DA26516A409; Tue, 18 Apr 2006 19:26:24 +0000 (UTC) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9AB3616A400 for ; Tue, 18 Apr 2006 19:26:24 +0000 (UTC) (envelope-from marcel@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6756A43D5E for ; Tue, 18 Apr 2006 19:26:24 +0000 (GMT) (envelope-from marcel@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.1/8.13.1) with ESMTP id k3IJQOPJ025373 for ; Tue, 18 Apr 2006 19:26:24 GMT (envelope-from marcel@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.1/8.13.1/Submit) id k3IJQOCf025367 for perforce@freebsd.org; Tue, 18 Apr 2006 19:26:24 GMT (envelope-from marcel@freebsd.org) Date: Tue, 18 Apr 2006 19:26:24 GMT Message-Id: <200604181926.k3IJQOCf025367@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to marcel@freebsd.org using -f From: Marcel Moolenaar To: Perforce Change Reviews Cc: Subject: PERFORCE change 95515 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Apr 2006 19:26:25 -0000 http://perforce.freebsd.org/chv.cgi?CH=95515 Change 95515 by marcel@marcel_nfs on 2006/04/18 19:25:40 Keep a bitmask of ports that use the serdev I/F. We use that in the interrupt handler to quickly assess pending interrupt status for those ports and service them in priority order. The bitmask is u_long on purpose. It allows for 32 ports on ILP32 machines and 64 ports on LP64 machines. The reason is to avoid 64-bit operations on ILP32 machines and given that puc(4) used to hardcode a limit of 16 ports before and PCI bus width is still mostly 32-bit in most cases so that interrupt latch registers (ILRs) are typically 32-bit wide it is not expected to be a problem on ILP32 machines, let alone LP64 machines. This may need to be revisited when cards with more than 32 ports become common (unlikely) and may need a revamp if boards with more than 64 ports need to be handled by puc(4). Affected files ... .. //depot/projects/uart/dev/puc/puc.c#27 edit .. //depot/projects/uart/dev/puc/puc_bfe.h#1 add Differences ... ==== //depot/projects/uart/dev/puc/puc.c#27 (text+ko) ==== @@ -494,8 +494,10 @@ i = 0, isrc = SER_INT_OVERRUN; while (i < PUC_ISRCCNT) { port->p_ihsrc[i] = SERDEV_IHAND(originator, isrc); - if (port->p_ihsrc[i] != NULL) + if (port->p_ihsrc[i] != NULL) { + sc->sc_serdevs |= 1UL << (port->p_nr - 1); port->p_ih = NULL; + } i++, isrc <<= 1; } }